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User's Manual
PD789407A, 789417A Subseries
8-Bit Single-Chip Microcontrollers
PD789405A PD789406A PD789407A
PD789415A PD789416A PD789417A PD78F9418A
Document No. U13952EJ3V0UD00 (3rd edition) Date Published April 2003 N CP(K)
1999, 2003 Printed in Japan
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[MEMO]
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NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
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These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited.
* The information in this document is current as of November, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).
M8E 02. 11-1
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Regional Information
Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
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J02.11
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Major Revisions in This Edition
Page pp.38, 39, 41 p.92 pp.112, 113 pp.151, 164 Description Modification of pin handling of AVREF pin and VPP pin in CHAPTER 2 PIN FUNCTIONS Addition of Note related to feedback resistor in Figure 5-3 Format of Suboscillation Mode Register Addition of 6.5 Cautions on Using 16-Bit Timer 50 Addition of (8) Input impedance of ANI0 to ANI6 pins in 10.5 Cautions on Using 8-Bit A/D Converter and 11.5 Cautions on Using 10-Bit A/D Converter Modification of description of (2) A/D conversion result register 0 (ADCR0) in 11.2 Configuration of 10-Bit A/D Converter Addition of description on reading receive data of UART in 13.4.2 Asynchronous serial interface (UART) mode Addition of Caution in Figure 15-2 Format of Interrupt Request Flag Register Addition of Caution in Figure 15-7 Format of Key Return Mode Register 00 Addition of description on pull-up resistor and divider resistor for LCD driving in Table 18-1 Differences Between PD78F9418A and Mask ROM Versions Overall revision of contents related to flash memory programming as 18.1 Flash Memory Characteristics Addition of CHAPTER 21 ELECTRICAL SPECIFICATIONS Addition of CHAPTER 22 CHARACTERISTICS CURVES (REFERENCE VALUES) Addition of CHAPTER 23 PACKAGE DRAWINGS Addition of CHAPTER 24 RECOMMENDED SOLDERING CONDITIONS Overall revision of contents of APPENDIX A DEVELOPMENT TOOLS Deletion of embedded software Addition of APPENDIX B NOTES ON TARGET SYSTEM DESIGN
p.154
p.196
p.232 p.237 p.256
pp.257 to 266 pp.278 to 292 pp.293 to 295 pp.296, 297 pp.298, 299 pp.300 to 309
pp.310 to 313
The mark
shows major revised points.
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INTRODUCTION
Target Readers
This manual is intended for users who wish to understand the functions of the
PD789407A and PD789417A Subseries and to design and develop application
systems and programs using these microcontrollers. Target products: * PD789407A Subseries: PD789405A, PD789406A, and PD789407A * PD789417A Subseries: PD789415A, PD789416A, PD789417A, and
PD78F9418A
Purpose This manual is intended to give users an understanding of the functions described in the Organization below. Organization The PD789407A and PD789417A Subseries User's Manual is divided into two parts: this manual and instructions (common to the 78K/0S Series).
PD789407A and PD789417A
Subseries User's Manual * Pin functions * Internal block functions * Interrupt functions * Other on-chip peripheral functions * Electrical specifications How to Read This Manual
78K/0S Series User's Manual Instructions * CPU function * Instruction set * Explanation of each instruction
It is assumed that the reader of this manual has general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. * To understand the functions in general: Read this manual in the order of the CONTENTS. * How to interpret the register formats: The name of a bit whose number is enclosed in brackets is reserved for the assembler and is defined for the C compiler by the header file sfrbit.h. * When you know a register name and want to confirm its details: Read APPENDIX C REGISTER INDEX. * To know the 78K/0S Series instructions functions in detail: Refer to 78K/0S Series Instructions User's Manual (U11047E). * To learn the electrical specifications of the PD789407A and PD789417A Subseries Refer to CHAPTER 21 ELECTRICAL SPECIFICATIONS.
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Conventions
Data significance: Active low representation: Note: Caution: Remark: Numerical representation:
Higher digits on the left and lower digits on the right xxx (overscore over pin or signal name) Footnote for item marked with Note in the text Information requiring particular attention Supplementary information Binary ... xxxx or xxxxB Decimal ... xxxx Hexadecimal ... xxxxH
Related Documents
The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name Document No. This manual U11047E
PD789407A, 789417A Subseries User's Manual
78K/0S Series Instructions User's Manual
Documents Related to Development Software Tools (User's Manuals)
Document Name RA78K0S Assembler Package Operation Language Structured Assembly Language CC78K0S C Compiler Operation Language SM78K Series System Simulator Ver. 2.30 or Later Operation (Windows Based) External Part User Open Interface Specifications ID78K Series Integrated Debugger Ver. 2.30 or Later Project Manager Ver. 3.12 or Later (Windows Based) Operation (Windows Based)
TM
Document No. U14876E U14877E U11623E U14871E U14872E U15373E U15802E U15185E U14610E
Documents Related to Development Hardware Tools (User's Manuals)
Document Name IE-78K0S-NS In-Circuit Emulator IE-78K0S-NS-A In-Circuit Emulator IE-789418-NS-EM1 Emulation Board Document No. U13549E U15207E U14364E
Caution
The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
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Documents Related to Flash Memory Writing
Document Name PG-FP3 Flash Memory Programmer User's Manual PG-FP4 Flash Memory Programmer User's Manual Document No. U13502E U15260E
Other Related Documents
Document Name SEMICONDUCTOR SELECTION GUIDE - Products and Packages Semiconductor Device Mount Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Document No. X13769X Note C11531E C10983E C11892E
Note See the "Semiconductor Device Mount Manual" webpage (http://www.necel.com/pkg/en/mount/index.html) Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
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CONTENTS
CHAPTER 1 GENERAL...........................................................................................................................23 1.1 Features .........................................................................................................................................23 1.2 Applications ..................................................................................................................................23 1.3 Ordering Information....................................................................................................................24 1.4 Pin Configuration (Top View) ......................................................................................................25 1.5 78K/0S Series Lineup ...................................................................................................................27 1.6 Block Diagram...............................................................................................................................30 1.7 Overview of Functions .................................................................................................................31 CHAPTER 2 PIN FUNCTIONS ...............................................................................................................33 2.1 List of Pin Functions ....................................................................................................................33 2.2 Description of Pin Functions.......................................................................................................36
2.2.1 P00 to P03 (Port 0) ........................................................................................................................... 36 2.2.2 P20 to P27 (Port 2) ........................................................................................................................... 36 2.2.3 P40 to P47 (Port 4) ........................................................................................................................... 37 2.2.4 P50 to P53 (Port 5) ........................................................................................................................... 37 2.2.5 P60 to P66 (Port 6) ........................................................................................................................... 37 2.2.6 P80 to P87 (Port 8) ........................................................................................................................... 38 2.2.7 P90 to P93 (Port 9) ........................................................................................................................... 38 2.2.8 S0 to S15 .......................................................................................................................................... 38 2.2.9 COM0 to COM3 ................................................................................................................................ 38 2.2.10 VLC0 to VLC2 .................................................................................................................................... 38 2.2.11 BIAS................................................................................................................................................ 38 2.2.12 AVREF ............................................................................................................................................. 38 2.2.13 AVDD ............................................................................................................................................... 38 2.2.14 AVSS ............................................................................................................................................... 39 2.2.15 RESET ............................................................................................................................................ 39 2.2.16 X1, X2 ............................................................................................................................................. 39 2.2.17 XT1, XT2......................................................................................................................................... 39 2.2.18 VDD0, VDD1 ....................................................................................................................................... 39 2.2.19 VSS0, VSS1 ....................................................................................................................................... 39 2.2.20 VPP (PD78F9418A only) ................................................................................................................ 39 2.2.21 IC (mask ROM version only) ........................................................................................................... 40
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins............................................41 CHAPTER 3 CPU ARCHITECTURE ......................................................................................................44 3.1 Memory Space...............................................................................................................................44
3.1.1 Internal program memory space ....................................................................................................... 48 3.1.2 Internal data memory space ............................................................................................................. 49 3.1.3 Special function register (SFR) area................................................................................................. 49 3.1.4 Data memory addressing .................................................................................................................. 50
3.2 Processor Registers .....................................................................................................................54
3.2.1 Control registers................................................................................................................................ 54
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3.2.2 General-purpose registers ................................................................................................................ 57 3.2.3 Special function registers (SFR) ....................................................................................................... 58
3.3 Instruction Address Addressing................................................................................................. 61
3.3.1 Relative addressing .......................................................................................................................... 61 3.3.2 Immediate addressing....................................................................................................................... 62 3.3.3 Table indirect addressing.................................................................................................................. 63 3.3.4 Register addressing.......................................................................................................................... 63
3.4 Operand Address Addressing..................................................................................................... 64
3.4.1 Direct addressing.............................................................................................................................. 64 3.4.2 Short direct addressing..................................................................................................................... 65 3.4.3 Special function register (SFR) addressing ...................................................................................... 66 3.4.4 Register addressing.......................................................................................................................... 67 3.4.5 Register indirect addressing ............................................................................................................. 68 3.4.6 Based addressing ............................................................................................................................. 69 3.4.7 Stack addressing .............................................................................................................................. 69
CHAPTER 4 PORT FUNCTIONS ........................................................................................................... 70 4.1 Function of Port ............................................................................................................................ 70 4.2 Configuration of Ports ................................................................................................................. 72
4.2.1 Port 0 ................................................................................................................................................ 72 4.2.2 Port 2 ................................................................................................................................................ 73 4.2.3 Port 4 ................................................................................................................................................ 78 4.2.4 Port 5 ................................................................................................................................................ 80 4.2.5 Port 6 ................................................................................................................................................ 81 4.2.6 Port 8 ................................................................................................................................................ 83 4.2.7 Port 9 ................................................................................................................................................ 84
4.3 Registers Controlling Ports ......................................................................................................... 85 4.4 Operation of Ports ........................................................................................................................ 88
4.4.1 Writing to I/O port.............................................................................................................................. 88 4.4.2 Reading from I/O port ....................................................................................................................... 88 4.4.3 Arithmetic operation of I/O port ......................................................................................................... 88
CHAPTER 5 CLOCK GENERATOR ...................................................................................................... 89 5.1 Functions of Clock Generator ..................................................................................................... 89 5.2 Configuration of Clock Generator............................................................................................... 89 5.3 Registers Controlling Clock Generator ...................................................................................... 91 5.4 System Clock Oscillators............................................................................................................. 94
5.4.1 Main system clock oscillator ............................................................................................................. 94 5.4.2 Subsystem clock oscillator................................................................................................................ 95 5.4.3 Examples of incorrect resonator connection..................................................................................... 96 5.4.4 Divider............................................................................................................................................... 97 5.4.5 When no subsystem clock is used.................................................................................................... 97
5.5 Operation of Clock Generator ..................................................................................................... 98 5.6 Changing Setting of System Clock and CPU Clock .................................................................. 99
5.6.1 Time required for switching between system clock and CPU clock.................................................. 99 5.6.2 Switching between system clock and CPU clock............................................................................ 100
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CHAPTER 6 16-BIT TIMER 50 .............................................................................................................101 6.1 Function of 16-Bit Timer 50 .......................................................................................................101 6.2 Configuration of 16-Bit Timer 50 ...............................................................................................102 6.3 Registers Controlling 16-Bit Timer 50 ......................................................................................104 6.4 Operation of 16-Bit Timer 50......................................................................................................107
6.4.1 Operation as timer interrupt ............................................................................................................ 107 6.4.2 Operation as timer output ............................................................................................................... 109 6.4.3 Capture operation ........................................................................................................................... 110 6.4.4 16-bit timer counter 50 readout....................................................................................................... 111
6.5 Cautions on Using 16-Bit Timer 50 ...........................................................................................112
6.5.1 Restrictions when rewriting 16-bit compare register 50 .................................................................. 112
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 00 TO 02..............................................................114 7.1 Function of 8-Bit Timer/Event Counters 00 to 02 ....................................................................114 7.2 Configuration of 8-Bit Timer/Event Counters 00 to 02............................................................115 7.3 Registers Controlling 8-Bit Timer/Event Counters 00 to 02 ...................................................118 7.4 Operation of 8-Bit Timer/Event Counters 00 to 02...................................................................122
7.4.1 Operation as interval timer.............................................................................................................. 122 7.4.2 Operation as external event counter (timer 00 and timer 01 only) .................................................. 125 7.4.3 Operation as square-wave output (timer 02 only) ........................................................................... 126
7.5 Cautions on Using 8-Bit Timer/Event Counters 00 to 02 ........................................................128 CHAPTER 8 WATCH TIMER................................................................................................................129 8.1 Functions of Watch Timer..........................................................................................................129 8.2 Configuration of Watch Timer ...................................................................................................130 8.3 Register Controlling Watch Timer.............................................................................................131 8.4 Operation of Watch Timer..........................................................................................................132
8.4.1 Operation as watch timer ................................................................................................................ 132 8.4.2 Operation as interval timer.............................................................................................................. 132
CHAPTER 9 WATCHDOG TIMER........................................................................................................134 9.1 Functions of Watchdog Timer ...................................................................................................134 9.2 Configuration of Watchdog Timer.............................................................................................135 9.3 Registers Controlling Watchdog Timer ....................................................................................136 9.4 Operation of Watchdog Timer ...................................................................................................138
9.4.1 Operation as watchdog timer .......................................................................................................... 138 9.4.2 Operation as interval timer.............................................................................................................. 139
CHAPTER 10 8-BIT A/D CONVERTER (PD789407A SUBSERIES)..............................................140 10.1 Function of 8-Bit A/D Converter ..............................................................................................140 10.2 Configuration of 8-Bit A/D Converter......................................................................................140 10.3 Registers Controlling 8-Bit A/D Converter .............................................................................143 10.4 Operation of 8-Bit A/D Converter ............................................................................................145
10.4.1 Basic operation of 8-bit A/D converter .......................................................................................... 145 10.4.2 Input voltage and conversion result .............................................................................................. 146 10.4.3 Operation mode of 8-bit A/D converter ......................................................................................... 148
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10.5 Cautions on Using 8-Bit A/D Converter.................................................................................. 149 CHAPTER 11 10-BIT A/D CONVERTER (PD789417A SUBSERIES) ........................................... 153 11.1 Function of 10-Bit A/D Converter............................................................................................ 153 11.2 Configuration of 10-Bit A/D Converter ................................................................................... 153 11.3 Registers Controlling 10-Bit A/D Converter........................................................................... 156 11.4 Operation of 10-Bit A/D Converter .......................................................................................... 158
11.4.1 Basic operation of 10-bit A/D converter ........................................................................................ 158 11.4.2 Input voltage and conversion result .............................................................................................. 160 11.4.3 Operation mode of 10-bit A/D converter ....................................................................................... 161
11.5 Cautions on Using 10-Bit A/D Converter................................................................................ 162 CHAPTER 12 COMPARATOR .............................................................................................................. 166 12.1 Functions of Comparator......................................................................................................... 166 12.2 Configuration of Comparator .................................................................................................. 167 12.3 Register Controlling Comparator............................................................................................ 168 12.4 Operation of Comparator......................................................................................................... 169 CHAPTER 13 SERIAL INTERFACE 00 .............................................................................................. 171 13.1 Functions of Serial Interface 00 .............................................................................................. 171 13.2 Configuration of Serial Interface 00........................................................................................ 172 13.3 Registers Controlling Serial Interface 00 ............................................................................... 176 13.4 Operation of Serial Interface 00............................................................................................... 183
13.4.1 Operation stopped mode .............................................................................................................. 183 13.4.2 Asynchronous serial interface (UART) mode................................................................................ 185 13.4.3 3-wire serial I/O mode................................................................................................................... 198
CHAPTER 14 LCD CONTROLLER/DRIVER ....................................................................................... 202 14.1 Functions of LCD Controller/Driver ........................................................................................ 202 14.2 Configuration of LCD Controller/Driver.................................................................................. 203 14.3 Registers Controlling LCD Controller/Driver ......................................................................... 205 14.4 Setting LCD Controller/Driver.................................................................................................. 208 14.5 LCD Display Data Memory ....................................................................................................... 208 14.6 Common and Segment Signals............................................................................................... 209 14.7 Supplying LCD Drive Voltages VLC0, VLC1, and VLC2 ............................................................. 213 14.8 Display Modes........................................................................................................................... 215
14.8.1 Static display example .................................................................................................................. 215 14.8.2 Two-time-slice display example .................................................................................................... 218 14.8.3 Three-time-slice display example ................................................................................................. 221 14.8.4 Four-time-slice display example ................................................................................................... 225
CHAPTER 15 INTERRUPT FUNCTIONS............................................................................................. 228 15.1 Interrupt Function Types ......................................................................................................... 228 15.2 Interrupt Sources and Configuration...................................................................................... 228 15.3 Registers Controlling Interrupt Function ............................................................................... 231 15.4 Operation of Interrupt Servicing ............................................................................................. 238
15.4.1 Non-maskable interrupt acknowledgment operation..................................................................... 238
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15.4.2 Maskable interrupt acknowledgment operation ............................................................................ 240 15.4.3 Multiple interrupt servicing ............................................................................................................ 241 15.4.4 Putting interrupt requests on hold ................................................................................................. 243
CHAPTER 16 STANDBY FUNCTION ..................................................................................................244 16.1 Standby Function and Configuration .....................................................................................244
16.1.1 Standby function ........................................................................................................................... 244 16.1.2 Standby function control register .................................................................................................. 245
16.2 Operation of Standby Function ...............................................................................................246
16.2.1 HALT mode ................................................................................................................................... 246 16.2.2 STOP mode .................................................................................................................................. 249
CHAPTER 17 RESET FUNCTION........................................................................................................252 CHAPTER 18 PD78F9418A.................................................................................................................256 18.1 Flash Memory Characteristics.................................................................................................257
18.1.1 Programming environment............................................................................................................ 257 18.1.2 Communication mode ................................................................................................................... 258 18.1.3 On-board pin connections............................................................................................................. 261 18.1.4 Connection when using flash memory writing adapter.................................................................. 264
CHAPTER 19 MASK OPTIONS............................................................................................................267 19.1 Mask Option for Pins ................................................................................................................267 19.2 Mask Option for Voltage Division Resistor for LCD Driver ..................................................267 CHAPTER 20 INSTRUCTION SET.......................................................................................................268 20.1 Operation ...................................................................................................................................268
20.1.1 Operand identifiers and description methods ............................................................................... 268 20.1.2 Description of "Operation" column ................................................................................................ 269 20.1.3 Description of "Flag" column ......................................................................................................... 269
20.2 Operation List............................................................................................................................270 20.3 Instructions Listed by Addressing Type ................................................................................275 CHAPTER 21 ELECTRICAL SPECIFICATIONS .................................................................................278 CHAPTER 22 CHARACTERISTICS CURVES (REFERENCE VALUES)..........................................293 22.1 Characteristics Curves for Mask ROM Versions ...................................................................293 22.2 Characteristics Curves for PD78F9418A ..............................................................................295 CHAPTER 23 PACKAGE DRAWINGS ................................................................................................296 CHAPTER 24 RECOMMENDED SOLDERING CONDITIONS ...........................................................298 APPENDIX A DEVELOPMENT TOOLS ...............................................................................................300 A.1 Software Package.......................................................................................................................302 A.2 Language Processing Software................................................................................................302 A.3 Control Software ........................................................................................................................303 14
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A.4 A.5 A.6 A.7
Flash Memory Writing Tools ..................................................................................................... 303 Debugging Tools (Hardware).................................................................................................... 304 Debugging Tools (Software) ..................................................................................................... 305 Package Drawings of Conversion Socket and Conversion Adapter .................................... 306
A.7.1 Package drawing and recommended footprint of conversion socket (EV-9200GC-80) ................. 306 A.7.2 Package drawing of conversion adapter (TGK-080SDW) .............................................................. 308 A.7.3 Package drawing of conversion adapter (TGC-080SBP) ............................................................... 309
APPENDIX B NOTES ON TARGET SYSTEM DESIGN ................................................................... 310 APPENDIX C REGISTER INDEX ......................................................................................................... 314 C.1 Register Index (Alphabetic Order of Register Name) ............................................................. 314 C.2 Register Index (Alphabetic Order of Register Symbol).......................................................... 316 APPENDIX D REVISION HISTORY ..................................................................................................... 318
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LIST OF FIGURES (1/5)
Figure No. 2-1 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 Title Page
Pin I/O Circuits ............................................................................................................................................ 42 Memory Map (PD789405A and PD789415A) ......................................................................................... 44 Memory Map (PD789406A and PD789416A) ......................................................................................... 45 Memory Map (PD789407A and PD789417A) ......................................................................................... 46 Memory Map (PD78F9418A) .................................................................................................................... 47 Data Memory Addressing (PD789405A and PD789415A)...................................................................... 50 Data Memory Addressing (PD789406A and PD789416A)...................................................................... 51 Data Memory Addressing (PD789407A and PD789417A)...................................................................... 52 Data Memory Addressing (PD78F9418A)................................................................................................. 53 Program Counter Configuration .................................................................................................................. 54 Program Status Word Configuration ........................................................................................................... 54 Stack Pointer Configuration ........................................................................................................................ 56 Data Saved to Stack Memory...................................................................................................................... 56 Data Restored from Stack Memory ............................................................................................................. 56 General-Purpose Register Configuration .................................................................................................... 57 Port Types ................................................................................................................................................... 70 Block Diagram of P00 to P03 ...................................................................................................................... 72 Block Diagram of P20.................................................................................................................................. 73 Block Diagram of P21.................................................................................................................................. 74 Block Diagram of P22 and P24 ................................................................................................................... 75 Block Diagram of P23.................................................................................................................................. 76 Block Diagram of P25 to P27 ...................................................................................................................... 77 Block Diagram of P40 to P45 ...................................................................................................................... 78 Block Diagram of P46 and P47 ................................................................................................................... 79 Block Diagram of P50 to P53 ...................................................................................................................... 80 Block Diagram of P60 and P61 ................................................................................................................... 81 Block Diagram of P62 to P66 ...................................................................................................................... 82 Block Diagram of P80 to P87 ...................................................................................................................... 83 Block Diagram of P90 to P93 ...................................................................................................................... 84 Format of Port Mode Register ..................................................................................................................... 86 Format of Pull-Up Resistor Option Register 0 ............................................................................................. 86 Format of Pull-Up Resistor Option Register 1 ............................................................................................. 87 Format of Pull-Up Resistor Option Register 2 ............................................................................................. 87 Block Diagram of Clock Generator.............................................................................................................. 90 Format of Processor Clock Control Register............................................................................................... 91 Format of Suboscillation Mode Register ..................................................................................................... 92 Format of Subclock Control Register .......................................................................................................... 93 External Circuit of Main System Clock Oscillator ........................................................................................ 94 External Circuit of Subsystem Clock Oscillator ........................................................................................... 95 Examples of Incorrect Resonator Connection............................................................................................. 96 Switching Between System Clock and CPU Clock ................................................................................... 100
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Figure No. 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 8-1 8-2 8-3 9-1 9-2 9-3 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 Title Page
Block Diagram of 16-Bit Timer 50 ..............................................................................................................102 Format of 16-Bit Timer Mode Control Register 50 .....................................................................................105 Format of Port Mode Register 2.................................................................................................................106 Settings of 16-Bit Timer Mode Control Register 50 for Timer Interrupt Operation .....................................107 Timing of Timer Interrupt Operation ...........................................................................................................108 Settings of 16-Bit Timer Mode Control Register 50 for Timer Output Operation........................................109 Timer Output Timing ..................................................................................................................................109 Settings of 16-Bit Timer Mode Control Register 50 for Capture Operation ................................................110 Capture Operation Timing (Both Edges of CPT5 Pin Are Specified) .........................................................110 Readout Timing of 16-Bit Timer Counter 50 ..............................................................................................111 Block Diagram of 8-Bit Timer/Event Counter 00 ........................................................................................116 Block Diagram of 8-Bit Timer/Event Counter 01 ........................................................................................116 Block Diagram of 8-Bit Timer 02 ................................................................................................................117 Format of 8-Bit Timer Mode Control Register 00 .......................................................................................118 Format of 8-Bit Timer Mode Control Register 01 .......................................................................................119 Format of 8-Bit Timer Mode Control Register 02 .......................................................................................120 Format of Port Mode Register 2.................................................................................................................121 Interval Timer Operation Timing of Timer 00 and Timer 01 .......................................................................123 Interval Timer Operation Timing of Timer 02 .............................................................................................124 External Event Counter Operation Timing (with Rising Edge Specified) ...................................................125 Square-Wave Output Timing......................................................................................................................127 Start Timing of 8-Bit Timer Counters 00, 01, and 02..................................................................................128 External Event Counter Operation Timing .................................................................................................128 Block Diagram of Watch Timer ..................................................................................................................129 Format of Watch Timer Mode Control Register..........................................................................................131 Watch Timer/Interval Timer Operation Timing ...........................................................................................133 Block Diagram of Watchdog Timer ............................................................................................................135 Format of Timer Clock Selection Register 2 ..............................................................................................136 Format of Watchdog Timer Mode Register ................................................................................................137 Block Diagram of 8-Bit A/D Converter........................................................................................................141 Format of A/D Converter Mode Register 0.................................................................................................143 Format of A/D Input Selection Register 0...................................................................................................144 Basic Operation of 8-Bit A/D Converter .....................................................................................................146 Relationship Between Analog Input Voltage and A/D Conversion Result..................................................147 Software-Started A/D Conversion ..............................................................................................................148 How to Reduce Current Consumption in Standby Mode............................................................................149 Conversion Result Readout Timing (When Conversion Result Is Undefined Value).................................150 Conversion Result Readout Timing (When Conversion Result Is Normal Value)......................................150 Analog Input Pin Processing ......................................................................................................................151 A/D Conversion End Interrupt Request Generation Timing .......................................................................152
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Figure No. 10-12 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 12-1 12-2 12-3 12-4 12-5 13-1 13-2 13-3 13-4 13-5 13-6 13-7 13-8 13-9 13-10 13-11 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10 14-11 Title Page
AVDD Pin Processing ................................................................................................................................. 152 Block Diagram of 10-Bit A/D Converter..................................................................................................... 154 Format of A/D Converter Mode Register 0................................................................................................ 156 Format of A/D Input Selection Register 0.................................................................................................. 157 Basic Operation of 10-Bit A/D Converter................................................................................................... 159 Relationship Between Analog Input Voltage and A/D Conversion Result................................................. 160 Software-Started A/D Conversion ............................................................................................................. 161 How to Reduce Current Consumption in Standby Mode........................................................................... 162 Conversion Result Readout Timing (When Conversion Result Is Undefined Value) ................................ 163 Conversion Result Readout Timing (When Conversion Result Is Normal Value)..................................... 163 Analog Input Pin Processing ..................................................................................................................... 164 A/D Conversion End Interrupt Request Generation Timing ...................................................................... 165 AVDD Pin Processing ................................................................................................................................. 165 Block Diagram of Comparator ................................................................................................................... 167 Format of Comparator Mode Register 0.................................................................................................... 168 Settings of Comparator Mode Register 0 for Comparator Operation ........................................................ 169 Settings of External Interrupt Mode Register 1 at INTCMP0 Occurrence ................................................. 169 Comparator Operation Timing................................................................................................................... 170 Block Diagram of Serial Interface 00......................................................................................................... 173 Block Diagram of Baud Rate Generator.................................................................................................... 174 Format of Serial Operation Mode Register 00........................................................................................... 176 Format of Asynchronous Serial Interface Mode Register 00..................................................................... 177 Format of Asynchronous Serial Interface Status Register 00 ................................................................... 179 Format of Baud Rate Generator Control Register 00................................................................................ 180 Format of Asynchronous Serial Interface Transmit/Receive Data ............................................................ 191 Asynchronous Serial Interface Transmission Completion Interrupt Timing............................................... 193 Asynchronous Serial Interface Reception Completion Interrupt Timing.................................................... 194 Receive Error Timing................................................................................................................................. 195 3-Wire Serial I/O Mode Timing .................................................................................................................. 201 Block Diagram of LCD Controller/Driver.................................................................................................... 204 Format of LCD Display Mode Register 0................................................................................................... 205 Format of LCD Port Selector 0 .................................................................................................................. 206 Format of LCD Clock Control Register 0................................................................................................... 207 Relationship Between LCD Display Data Memory Contents and Segment/Common Outputs ................. 208 Common Signal Waveforms...................................................................................................................... 211 Voltages and Phases of Common and Segment Signals.......................................................................... 212 Examples of LCD Drive Power Connections (with On-Chip Voltage Divider Resistors) ........................... 214 Static LCD Display Pattern and Electrode Connections............................................................................ 215 Example of Connecting Static LCD Panel................................................................................................. 216 Static LCD Drive Waveform Examples...................................................................................................... 217
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LIST OF FIGURES (4/5)
Figure No. 14-12 14-13 14-14 14-15 14-16 14-17 14-18 14-19 14-20 14-21 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 15-9 15-10 15-11 15-12 15-13 15-14 15-15 16-1 16-2 16-3 16-4 16-5 17-1 17-2 17-3 17-4 18-1 18-2 18-3 18-4 18-5 Title Page
Two-Time-Slice LCD Display Pattern and Electrode Connections ............................................................218 Example of Connecting Two-Time-Slice LCD Panel..................................................................................219 Two-Time-Slice LCD Drive Waveform Examples (1/2 Bias Method) .........................................................220 Three-Time-Slice LCD Display Pattern and Electrode Connections..........................................................221 Example of Connecting Three-Time-Slice LCD Panel ...............................................................................222 Three-Time-Slice LCD Drive Waveform Examples (1/2 Bias Method).......................................................223 Three-Time-Slice LCD Drive Waveform Examples (1/3 Bias Method).......................................................224 Four-Time-Slice LCD Display Pattern and Electrode Connections............................................................225 Example of Connecting Four-Time-Slice LCD Panel .................................................................................226 Four-Time-Slice LCD Drive Waveform Examples (1/3 Bias Method).........................................................227 Basic Configuration of Interrupt Function...................................................................................................230 Format of Interrupt Request Flag Register.................................................................................................232 Format of Interrupt Mask Flag Register .....................................................................................................233 Format of External Interrupt Mode Register 0............................................................................................234 Format of External Interrupt Mode Register 1............................................................................................235 Configuration of Program Status Word ......................................................................................................236 Format of Key Return Mode Register 00 ...................................................................................................237 Block Diagram of Falling Edge Detector ....................................................................................................237 Flowchart of Non-Maskable Interrupt Request Acknowledgment ..............................................................239 Timing of Non-Maskable Interrupt Request Acknowledgment ...................................................................239 Non-Maskable Interrupt Request Acknowledgment...................................................................................239 Interrupt Acknowledgment Program Algorithm...........................................................................................240 Interrupt Request Acknowledgment Timing (Example: MOV A, r) .............................................................241 Interrupt Request Acknowledgment Timing (When Interrupt Request Flag Is Generated in Final Clock Under Execution) ...........................................................................................241 Example of Multiple Interrupt .....................................................................................................................242 Format of Oscillation Stabilization Time Selection Register.......................................................................245 Releasing HALT Mode by Interrupt............................................................................................................247 Releasing HALT Mode by RESET Input ....................................................................................................248 Releasing STOP Mode by Interrupt ...........................................................................................................250 Releasing STOP Mode by RESET Input....................................................................................................251 Block Diagram of Reset Function...............................................................................................................252 Reset Timing by RESET Input ...................................................................................................................253 Reset Timing by Overflow in Watchdog Timer...........................................................................................253 Reset Timing by RESET Input in STOP Mode...........................................................................................253 Environment for Writing Program to Flash Memory ...................................................................................257 Communication Mode Selection Format ....................................................................................................258 Example of Connection with Dedicated Flash Programmer.......................................................................259 VPP Pin Connection Example .....................................................................................................................261 Signal Conflict (Serial Interface Input Pin) .................................................................................................262
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Figure No. 18-6 18-7 18-8 18-9 18-10 Title Page
Malfunction of Another Device .................................................................................................................. 262 Signal Conflict (RESET Pin)...................................................................................................................... 263 Example of Flash Memory Writing Adapter Connection When Using 3-Wire Serial I/O Mode.................. 264 Example of Flash Memory Writing Adapter Connection When Using UART Mode .................................. 265 Example of Flash Memory Writing Adapter Connection When Using Pseudo 3-Wire Mode (When P0 Is Used) .................................................................................................................................... 266
A-1 A-2 A-3 A-4 A-5 B-1 B-2 B-3 B-4
Development Tools ................................................................................................................................... 301 Package Drawing of EV-9200GC-80 (for Reference) ............................................................................... 306 Recommended Footprint of EV-9200GC-80 (for Reference) .................................................................... 307 Package Drawing of TGK-080SDW (for Reference) ................................................................................. 308 Package Drawing of TGC-080SBP (for Reference) .................................................................................. 309 Distance Between In-Circuit Emulator and Conversion Socket (80GC).................................................... 310 Connection Condition of Target System (NP-80GC-TQ)........................................................................... 311 Distance Between In-Circuit Emulator and Conversion Adapter (80GK) .................................................. 312 Connection Condition of Target System (NP-80GK)................................................................................. 313
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LIST OF TABLES (1/2)
Table No. 2-1 3-1 3-2 3-3 4-1 4-2 4-3 5-1 5-2 6-1 6-2 6-3 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 8-1 8-2 8-3 9-1 9-2 9-3 9-4 9-5 10-1 11-1 12-1 13-1 Title Page
Types of Pin I/O Circuits ..............................................................................................................................41 Internal ROM Capacity.................................................................................................................................48 Vector Table.................................................................................................................................................48 Special Function Register List .....................................................................................................................59 Port Functions ..............................................................................................................................................71 Configuration of Port ....................................................................................................................................72 Port Mode Register and Output Latch Settings When Using Alternate Functions .......................................85 Configuration of Clock Generator.................................................................................................................89 Maximum Time Required for Switching CPU Clock .....................................................................................99 Configuration of 16-Bit Timer 50 ................................................................................................................102 Interval Time of 16-Bit Timer 50.................................................................................................................107 Settings of Capture Edge ...........................................................................................................................110 Interval Time of 8-Bit Timer/Event Counter 00...........................................................................................114 Interval Time of 8-Bit Timer/Event Counter 01...........................................................................................114 Interval Time of 8-Bit Timer 02...................................................................................................................114 Square-Wave Output Range of 8-Bit Timer 02 ..........................................................................................115 Configuration of 8-Bit Timer/Event Counters 00 to 02 ...............................................................................115 Interval Time of 8-Bit Timer/Event Counter 00...........................................................................................122 Interval Time of 8-Bit Timer/Event Counter 01...........................................................................................122 Interval Time of 8-Bit Timer 02...................................................................................................................123 Square-Wave Output Range of 8-Bit Timer 02 ..........................................................................................126 Interval Time of Interval Timer ...................................................................................................................130 Configuration of Watch Timer ....................................................................................................................130 Interval Time of Interval Timer ...................................................................................................................132 Program Loop Detection Time of Watchdog Timer ....................................................................................134 Interval Time ..............................................................................................................................................134 Configuration of Watchdog Timer ..............................................................................................................135 Program Loop Detection Time of Watchdog Timer ....................................................................................138 Interval Time of Interval Timer ...................................................................................................................139 Configuration of 8-Bit A/D Converter..........................................................................................................140 Configuration of 10-Bit A/D Converter........................................................................................................153 INTCMP0 Valid Edges ...............................................................................................................................169 Configuration of Serial Interface 00............................................................................................................172
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LIST OF TABLES (2/2)
Table No. 13-2 13-3 13-4 13-5 13-6 13-7 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10 15-1 15-2 15-3 16-1 16-2 16-3 16-4 17-1 18-1 18-2 18-3 19-1 19-2 20-1 24-1 Title Page
Operation Mode Settings of Serial Interface 00 ........................................................................................ 178 Example of Relationship Between Main System Clock and Baud Rate.................................................... 181 Relationship Between ASCK Pin Input Frequency and Baud Rate (When BRGC00 Is Set to 80H)......... 182 Example of Relationship Between Main System Clock and Baud Rate.................................................... 189 Relationship Between ASCK Pin Input Frequency and Baud Rate (When BRGC00 Is Set to 80H)......... 190 Receive Error Causes ............................................................................................................................... 195 Maximum Number of Pixels ...................................................................................................................... 202 Configuration of LCD Controller/Driver...................................................................................................... 203 Frame Frequencies (Hz) ........................................................................................................................... 207 COM Signals ............................................................................................................................................. 209 LCD Drive Voltage..................................................................................................................................... 210 LCD Drive Voltages (with On-Chip Voltage Divider Resistors) ................................................................. 213 Select and Deselect Voltages (COM0)...................................................................................................... 215 Select and Deselect Voltages (COM0 and COM1) ................................................................................... 218 Select and Deselect Voltages (COM0 to COM2) ...................................................................................... 221 Select and Deselect Voltages (COM0 to COM3) ...................................................................................... 225 Interrupt Source List.................................................................................................................................. 229 Flags Corresponding to Interrupt Request Signal Name........................................................................... 231 Time from Generation of Maskable Interrupt Request to Servicing .......................................................... 240 HALT Mode Operating Status ................................................................................................................... 246 Operation After Release of HALT Mode.................................................................................................... 248 STOP Mode Operating Status................................................................................................................... 249 Operation After Release of STOP Mode ................................................................................................... 251 Hardware Status After Reset..................................................................................................................... 254 Differences Between PD78F9418A and Mask ROM Versions................................................................ 256 Communication Mode List......................................................................................................................... 258 Pin Connection List ................................................................................................................................... 260 Selection of Mask Option for Pins ............................................................................................................. 267 Combination of Selectable Voltage Division Resistor ............................................................................... 267 Operand Identifiers and Description Methods ........................................................................................... 268 Surface Mounting Type Soldering Conditions ........................................................................................... 298
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CHAPTER 1 GENERAL
1.1 Features
* ROM and RAM capacities
Item Program Memory Data Memory Internal High-Speed RAM ROM 12 KB 16 KB 24 KB Flash memory 32 KB 512 bytes LCD Data RAM
Part Number
PD789405A, 789415A PD789406A, 789416A PD789407A, 789417A PD78F9418A
28 x 4 bits
* Minimum instruction execution time can be changed from high speed (0.4 s: @ 5.0 MHz operation with main system clock) to ultra low speed (122 s: @ 32.768 kHz operation with subsystem clock) * 43 I/O ports * Serial interface channel: Switchable between 3-wire serial I/O and UART modes * LCD controller/driver:
* Up to 28 segment signal outputs * Up to 4 common signal outputs * Bias switchable between 1/2 and 1/3
* Seven A/D converters with an 8-bit resolution (for PD789407A Subseries only) * Seven A/D converters with a 10-bit resolution (for PD789417A Subseries only) * Six timers:
* 16-bit timer * Two 8-bit timer/event counters * 8-bit timer * Watch timer * Watchdog timer
* 17 vectored interrupt sources * Power supply voltage: VDD = 1.8 to 5.5 V * Operating ambient temperature: TA = -40 to +85C
1.2 Applications
APS compact cameras, manometers, rice cookers, etc.
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CHAPTER 1 GENERAL
1.3 Ordering Information
Part Number Package 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) Internal ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Flash memory Flash memory
PD789405AGC-xxx-8BT PD789405AGK-xxx-9EU PD789406AGC-xxx-8BT PD789406AGK-xxx-9EU PD789407AGC-xxx-8BT PD789407AGK-xxx-9EU PD789415AGC-xxx-8BT PD789415AGK-xxx-9EU PD789416AGC-xxx-8BT PD789416AGK-xxx-9EU PD789417AGC-xxx-8BT PD789417AGK-xxx-9EU PD78F9418AGC-8BT PD78F9418AGK-9EU
Remark
xxx indicates ROM code suffix.
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CHAPTER 1 GENERAL
1.4 Pin Configuration (Top View)
* 80-pin plastic QFP (14 x 14) * 80-pin plastic TQFP (fine pitch) (12 x 12)
PD789405AGC-xxx-8BT PD789406AGC-xxx-8BT PD789407AGC-xxx-8BT PD789415AGC-xxx-8BT PD789416AGC-xxx-8BT PD789417AGC-xxx-8BT PD78F9418AGC-8BT
P40/KR0 P41/KR1 P42/KR2 P43/KR3 P44/KR4 P45/KR5 IC (VPP)
PD789405AGK-xxx-9EU PD789406AGK-xxx-9EU PD789407AGK-xxx-9EU PD789415AGK-xxx-9EU PD789416AGK-xxx-9EU PD789417AGK-xxx-9EU PD78F9418AGK-9EU
RESET
VDD0
VSS0
XT1
XT2
P46
P47
P00
P01
P02
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 VDD1 BIAS VLC0 VLC1 VLC2 VSS1 COM0 COM1 COM2 COM3 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 P50 P51 P52 P53 P20/SCK/ASCK P21/SO/TxD P22/SI/RxD P23/CMPTOUT0/TO2 P24/INTP0/TI0 P25/INTP1/TI1 P26/INTP2/TO5 P27/INTP3/CPT5 AVSS P60/ANI0/CMPIN0 P61/ANI1/CMPREF0 P62/ANI2 P63/ANI3 P64/ANI4 P65/ANI5 P66/ANI6
41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P93/S16
P92/S17
P91/S18
P90/S19
P87/S20
P86/S21
P85/S22
P84/S23
P83/S24
P82/S25
P81/S26
Cautions 1. Connect the IC (Internally Connected) pin directly to VSS0 or VSS1. 2. Connect the AVDD pin to VDD0. 3. Connect the AVSS pin to VSS0. Remark The parenthesized values apply to the PD78F9418A.
P80/S27
AVREF
AVDD
S10
S11
S12
S13
S14
S15
P03
X1
X2
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CHAPTER 1 GENERAL
ANI0 to ANI6: ASCK: AVDD: AVREF: AVSS: BIAS: CMPIN0: CMPREF0: CMPTOUT0:
Analog input Asynchronous serial input Analog power supply Analog reference voltage Analog ground LCD power supply bias control Comparator input Comparator reference Comparator output
P60 to P66: P80 to P87: P90 to P93: RESET: RxD: S0 to S27: SCK: SI: SO: TI0, TI1: TO2, TO5: TxD: VDD0, VDD1: VLC0 to VLC2: VPP: VSS0, VSS1: X1, X2: XT1, XT2:
Port 6 Port 8 Port 9 Reset Receive data Segment output Serial clock Serial input Serial output Timer input Timer output Transmit data Power supply LCD power supply Programming power supply Ground Crystal (main system clock) Crystal (subsystem clock)
COM0 to COM3: Common output CPT5: IC: Capture trigger input Internally connected
INTP0 to INTP3: Interrupt from peripherals KR0 to KR5: P00 to P03: P20 to P27: P40 to P47: P50 to P53: Key return Port 0 Port 2 Port 4 Port 5
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CHAPTER 1 GENERAL
1.5 78K/0S Series Lineup
The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.
Products in mass production Y subseries supports SMB. Small-scale package, general-purpose applications 44-pin 42-/44-pin 30-pin 30-pin 28-pin 20-pin 20-pin Products under development
PD789046 PD789026 PD789088 PD789074 PD789014 PD789062 PD789052
PD789074 with subsystem clock added PD789014 with enhanced timer function and expanded ROM and RAM PD789074 with enhanced timer function and expanded ROM and RAM PD789026 with enhanced timer function
On-chip UART and capable of low-voltage (1.8 V) operation RC oscillation version of PD789052 PD789860 without EEPROMTM, POC, and LVI
Small-scale package, general-purpose applications and A/D function 44-pin 44-pin 30-pin 30-pin 30-pin 30-pin 30-pin 30-pin
PD789177 PD789167 PD789156 PD789146 PD789134A PD789124A PD789114A PD789104A
LCD drive
PD789177Y PD789167Y
PD789167 with 10-bit A/D PD789104A with enhanced timer function PD789146 with 10-bit A/D PD789104A with EEPROM added PD789124A with 10-bit A/D RC oscillation version of PD789104A PD789104A with 10-bit A/D PD789026 with 8-bit A/D and multiplier added
144-pin 88-pin 80-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 52-pin 52-pin USB 44-pin
78K/0S Series
PD789835 PD789830 PD789489 PD789479 PD789417A PD789407A PD789456 PD789446 PD789436 PD789426 PD789316 PD789306 PD789467 PD789327
UART + 8-bit A/D + dot LCD (total display outputs: 96) UART + dot LCD (40 x 16) SIO + 10-bit A/D + internal voltage boosting method LCD (28 x 4) SIO + 8-bit A/D + resistance division method LCD (28 x 4)
PD789407A with 10-bit A/D
PD789446 with 10-bit A/D PD789426 with 10-bit A/D
SIO + 8-bit A/D + resistance division method LCD (28 x 4) SIO + 8-bit A/D + internal voltage boosting method LCD (15 x 4)
SIO + 8-bit A/D + internal voltage boosting method LCD (5 x 4) RC oscillation version of PD789306 SIO + internal voltage boosting method LCD (24 x 4) 8-bit A/D + internal voltage boosting method LCD (23 x 4) SIO + resistance division method LCD (24 x 4)
PD789800
Inverter control
For PC keyboard. On-chip USB function
44-pin
PD789842
On-chip bus controller
On-chip inverter controller and UART
30-pin
PD789850
Keyless entry
On-chip CAN controller
30-pin 20-pin 20-pin
PD789862 PD789861 PD789860
VFD drive
PD789860 with enhanced timer function, SIO, and expanded ROM and RAM RC oscillation version of PD789860
On-chip POC and key return circuit
52-pin
PD789871
Meter control
On-chip VFD controller (total display outputs: 25)
64-pin
PD789881
UART + resistance division method LCD (26 x 4)
TM
Remark VFD (Vacuum Fluorescent Display) is referred to as FIP documents, but the functions of the two are the same.
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(Fluorescent Indicator Panel) in some
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CHAPTER 1 GENERAL
The major functional differences between the subseries are listed below. Series for general-purpose applications and LCD drive
Function Subseries Smallscale package, generalpurpose applications 8-Bit 10-Bit ROM Timer A/D Capacity 8-Bit 16-Bit Watch WDT A/D (Bytes) 16 K 4 K to 16 K 16 K to 32 K 3 ch 2 K to 8 K 2 K to 4 K 4K 1 ch 2 ch - - 22 14 RC-oscillation version - 16 K to 24 K 3 ch 8 K to 16 K 1 ch 2 K to 8 K 1 ch 1 ch - 1 ch - 8 ch - 4 ch - 4 ch - 4 ch 24 K to 60 K 6 ch 24 K 24 K to 48 K 12 K to 24 K 12 K to 16 K 2 ch 1 ch 32 K to 48 K 3 ch 8 ch - 7 ch - 6 ch - 6 ch 8 K to 16 K - - 1 ch 1 ch 1 ch 3 ch - 8 ch - 7 ch - 6 ch - 6 ch - 2 ch (UART: 1 ch) 23 RC-oscillation version - 4 K to 24 K - 1 ch - 1 ch - 18 21 40 30 1 ch (UART: 1 ch) 43 2 ch (UART: 1 ch) 8 ch - 4 ch - 4 ch - 4 ch - - 1 ch (UART: 1 ch) 37 30 45 1.8 VNote Dot LCD supported 2.7 V 1.8 V - 20 On-chip EEPROM RC-oscillation version - 1 ch (UART: 1 ch) 31 1.8 V - 1 ch 1 ch 1 ch - 24 1 ch - - Serial Interface I/O VDD
MIN.Value
Remarks
PD789046 PD789026 PD789088 PD789074 PD789014 PD789062 PD789052
1 ch (UART: 1 ch)
34
1.8 V
-
Smallscale package, generalpurpose applications + A/D converter LCD drive
PD789177 PD789167 PD789156 PD789146 PD789134A PD789124A PD789114A PD789104A PD789835 PD789830 PD789489 PD789479 PD789417A PD789407A PD789456 PD789446 PD789436 PD789426 PD789316 PD789306 PD789467 PD789327
Note Flash memory version: 3.0 V
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Series for ASSP
Function Subseries USB
Inverter control On-chip bus controller
CHAPTER 1 GENERAL
8-Bit 10-Bit ROM Timer A/D Capacity 8-Bit 16-Bit Watch WDT A/D (Bytes) 8K 2 ch - - 1 ch 1 ch 1 ch - 8 ch 4 ch - - - 8 K to 16 K 3 ch Note 1 1 ch 16 K 1 ch 1 ch -
Serial Interface
I/O
VDD
MIN.Value
Remarks
PD789800 PD789842 PD789850
2 ch (USB: 1 ch) 1 ch (UART: 1 ch) 2 ch (UART: 1 ch)
31 30 18
4.0 V 4.0 V 4.0 V
- - -
Keyless entry
PD789861
4K
2 ch
-
-
1 ch
-
-
-
14
1.8 V
RC-oscillation version, on-chip EEPROM
PD789860 PD789862
VFD drive Meter control 16 K 1 ch 2 ch - 1 ch 1 ch - 1 ch 1 ch - - - - 1 ch (UART: 1 ch) 1 ch 1 ch (UART: 1 ch) 22 33 2.7 V 28 2.7 VNote 2
On-chip EEPROM - -
PD789871 PD789881
4 K to 8 K 3 ch 16 K 2 ch
Notes 1. 10-bit timer: 1 channel 2. Flash memory version: 3.0 V
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CHAPTER 1 GENERAL
1.6 Block Diagram
8-bit timer event/counter 00 8-bit timer event/counter 01
TI0/P24
Port 0
P00 to P03
TI1/P25
Port 2
P20 to P27
TO2/P23
8-bit timer 02
Port 4
P40 to P47
TO5/P26 CPT5/P27
16-bit timer 50
Port 5
P50 to P53
Watch timer
78K/0S CPU core
ROM (flash memory)
Port 6
P60 to P66
Watchdog timer
Port 8
P80 to P87
SCK/ASCK/P20 SO/TxD/P21 SI/RxD/P22 ANI0/P60 ANI1/P61 ANI2/P62 to ANI6/P66 AVDD AVSS AVREF S0 to S15 S16/P93 to S19/P90 S20/P87 to S27/P80 COM0 to COM3 VLC0 to VLC2 BIAS
Serial interface RAM
Port 9
P90 to P93
System control A/D converter
RESET X1 X2 XT1 XT2 INTP0/P24 INTP1/P25 INTP2/P26 INTP3/P27 KR0/P40 to KR5/P45 CMPTOUT0/P23 CMPIN0/P60 CMPREF0/P61
Interrupt control
LCD controller/driver
Comparator
VDD0 VDD1
VSS0 VSS1
IC (VPP)
Remarks 1. The internal ROM capacity varies depending on the product. 2. The parenthesized values apply to the PD78F9418A.
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1.7 Overview of Functions
Part Number Item Internal memory ROM
PD789405A PD789415A
Mask ROM 12 KB
PD789406A PD789416A
PD789407A PD789417A
PD78F9418A
Flash memory 16 KB 24 KB 32 KB
High-speed RAM LCD data RAM Minimum instruction execution time
512 bytes 28 x 4 bits * 0.4/1.6 s (@ 5.0 MHz operation with main system clock) * 122 s (@ 32.768 kHz operation with subsystem clock) 8 bits x 8 registers * 16-bit operations * Bit manipulation (set, reset, and test) Total of 43 port pins * 7 CMOS input pins * 32 CMOS I/O pins * 4 N-ch open-drain pins (12 V withstanding voltage)
General-purpose registers Instruction set
I/O ports
A/D converters
* Seven channels with 8-bit resolution (for PD789407A Subseries) * Seven channels with 10-bit resolution (for PD789417A Subseries) With timer output control function Switchable between 3-wire serial I/O and UART modes * Up to 28 segment signal outputs * Up to 4 common signal outputs * Bias switchable between 1/2 and 1/3 * * * * * 16-bit timer: 8-bit timer: 8-bit timer/event counters: Watch timer: Watchdog timer: 1 channel 1 channel 2 channels 1 channel 1 channel
Comparator Serial interface LCD controller/driver
Timers
Timer output Vectored interrupt sources Power supply voltage Operating ambient temperature Package Maskable Non-maskable
2 outputs Internal: 11, external: 5 Internal: 1 VDD = 1.8 to 5.5 V TA = -40 to +85C * 80-pin plastic QFP (14 x 14) * 80-pin plastic TQFP (fine pitch) (12 x 12)
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An outline of the timer is shown below.
16-Bit Timer 50 8-Bit Timer/Event Counters 00, 01 1 channel 1 channel 8-Bit Timer 02 Watch Timer Watchdog Timer
Operation mode
Interval timer External event counter Timer outputs Square-wave outputs Capture Interrupt sources
- -
1 channel -
1 channelNote 1 -
1 channelNote 2 -
Function
1 -
- -
1 1
- -
- -
1 input 1
- 1
- 1
- 2
- 2
Notes 1. The watch timer can perform both watch timer and interval timer functions at the same time. 2. The watchdog timer has watchdog timer and interval timer functions. However, use the watchdog timer by selecting either the watchdog timer function or interval timer function.
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2.1 List of Pin Functions
(1) Port pins
I/O I/O Function Port 0. 4-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, use of an on-chip pull-up resistor can be specified by setting pull-up resistor option register 0 (PU0). Port 2. 8-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, use of an on-chip pull-up resistor can be specified by setting pull-up resistor option register 1 (PU1). After Reset Input Alternate Function -
Pin Name P00 to P03
P20 P21 P22 P23 P24 P25 P26 P27 P40 to P45
I/O
Input
SCK/ASCK SO/TxD SI/RxD CMPTOUT0/TO2 INTP0/TI0 INTP1/TI1 INTP2/TO5 INTP3/CPT5
I/O
P46, P47
Port 4. 8-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, use of an on-chip pull-up resistor can be specified by setting pull-up resistor option register 0 (PU0). Port 5. 4-bit N-ch open-drain I/O port. Input/output can be specified in 1-bit units. For a mask ROM version, use of an on-chip pull-up resistor can be specified by the mask option. Port 6. 7-bit input port.
Input
KR0 to KR5
-
P50 to P53
I/O
Input
-
P60 P61 P62 to P66 P80 to P87
Input
Input
ANI0/CMPIN0 ANI1/CMPREF0 ANI2 to ANI6
I/O
Port 8. 8-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, use of an on-chip pull-up resistor can be specified by setting pull-up resistor option register 2 (PU2). Port 9. 4-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, use of an on-chip pull-up resistor can be specified by setting pull-up resistor option register 2 (PU2).
Input
S27 to S20
P90 to P93
I/O
Input
S19 to S16
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(2)
Non-port pins (1/2)
I/O Input Function External interrupt input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified After Reset Input Alternate Function P24/TI0 P25/TI1 P26/TO5 P27/CPT5 Input Input Output I/O Input Input Output Input Input Output Output Input Output Input Input Input Key return signal detection Serial interface serial data input Serial interface serial data output Serial interface serial clock input/output Serial clock input for asynchronous serial interface Serial data input for asynchronous serial interface Serial data output for asynchronous serial interface External count clock input to 8-bit timer (TM00) External count clock input to 8-bit timer (TM01) 8-bit timer (TM02) output 16-bit timer (TM50) output Capture edge input Comparator output Comparator input Comparator reference voltage input A/D converter analog input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input P40 to P45 P22/RxD P21/TxD P20/ASCK P20/SCK P22/SI P21/SO P24/INTP0 P25/INTP1 P23/CMPTOUT0 P26/INTP2 P27/INTP3 P23/TO2 P60/ANI0 P61/ANI1 P60/CMPIN0 P61/CMPREF0 P62 to P66 - - - Output A/D converter reference voltage A/D converter ground potential A/D converter analog power supply LCD controller/driver segment signal output - - - Output Input *-* *-* *-* *-* P93 to P90 P87 to P80 Output - - Input - Input - Input System reset input Input Connecting crystal resonator for subsystem clock oscillation LCD controller/driver common signal output LCD driving voltage Supply voltage for LCD driving Connecting crystal resonator for main system clock oscillation Output - - - - - - - *-* *-* *-* *-* *-* *-* *-*
Pin Name INTP0 INTP1 INTP2 INTP3 KR0 to KR5 SI SO SCK ASCK RxD TxD TI0 TI1 TO2 TO5 CPT5 CMPTOUT0 CMPIN0 CMPREF0 ANI0 ANI1 ANI2 to ANI6 AVREF AVSS AVDD S0 to S15 S16 to S19 S20 to S27 COM0 to COM3 VLC0 to VLC2 BIAS X1 X2 XT1 XT2 RESET
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(2)
Non-port pins (2/2)
I/O - - - - - - Function Positive power supply for ports Positive power supply for circuits other than ports Ground potential for ports Ground potential of circuits other than ports Internally connected. Connect directly to VSS0 or VSS1. Sets flash memory programming mode. Applies high voltage when a program is written or verified. After Reset - - - - - - Alternate Function *-* *-* *-* *-* *-* *-*
Pin Name VDD0 VDD1 VSS0 VSS1 IC VPP
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2.2 Description of Pin Functions
2.2.1 P00 to P03 (Port 0) These pins constitute a 4-bit I/O port and can be set to input or output port mode in 1-bit units by using port mode register 0 (PM0). When these pins are used as input port pins, an on-chip pull-up resistor can be used by setting pull-up resistor option register 0 (PU0). 2.2.2 P20 to P27 (Port 2) These pins constitute an 8-bit I/O port. In addition to I/O port pins, these pins can also function as the data and clock I/O of the serial interface, external interrupt input, and timer I/O. The following operation modes can be specified in 1-bit units. (1) Port mode In this mode, P20 to P27 function as an 8-bit I/O port. These pins can be set to input or output mode in 1-bit units by using port mode register 2 (PM2). When used as input port pins, an on-chip pull-up resistor can be used by setting pull-up resistor option register 1 (PU1). (2) Control mode In this mode, P20 to P27 function as the data I/O and the clock I/O of the serial interface, the external interrupt input, and timer I/O. (a) SI, SO These are the serial data I/O pins of the serial interface. (b) SCK This is the serial clock I/O pin of the serial interface. (c) RxD, TxD These are the serial data I/O pins of the asynchronous serial interface. (d) ASCK This is the serial clock input pin of the asynchronous serial interface. (e) TI0, TI1 These are external clock input pins for the 8-bit timer/event counter. (f) TO2 This is the output pin of the 8-bit timer. (g) TO5 This is the output pin of the 16-bit timer. (h) CPT5 This is the capture edge input pin.
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(i)
INTP0 to INTP3 These are external interrupt input pins for which a valid edge (rising edge, falling edge, or both rising and falling edges) can be specified.
(j)
CMPTOUT0 This is the comparator output pin.
Caution
When using P20 to P27 as serial interface pins, the I/O mode and output latch must be set according to the function to be used. For details of the setting, refer to Table 13-2.
2.2.3 P40 to P47 (Port 4) These pins constitute an 8-bit I/O port. In addition to I/O port pins, these pins can also function as key return signal detection pins. The following operation modes can be specified in 1-bit units. (1) Port mode In this mode, P40 to P47 function as an 8-bit I/O port. These pins can be set to input or output mode in 1-bit units by using port mode register 4 (PM4). When used as input port pins, an on-chip pull-up resistor can be used by setting pull-up resistor option register 0 (PU0). (2) Control mode In this mode, the pins function as key return signal detection pins (KR0 to KR5). 2.2.4 P50 to P53 (Port 5) These pins constitute a 4-bit N-channel open-drain I/O port. In the mask ROM version, it is possible to specify that pull-up resistors be used, via a mask option. 2.2.5 P60 to P66 (Port 6) These pins constitute a 7-bit input-only port. In addition to general-purpose input port pins, these pins can also function as A/D converter analog input pins and comparator input pins. (1) Port mode In this port mode, P60 to P66 function as a 7-bit input-only port. (2) Control mode In this mode, the pins can be used as A/D converter analog inputs and comparator inputs. (a) ANI0 to ANI6 These are the A/D converter analog input pins. (b) CMPIN0 This is the comparator input pin. (c) CMPREF0 This is the comparator reference voltage input pin.
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2.2.6 P80 to P87 (Port 8) These pins constitute an 8-bit I/O port. controller/driver segment signal. The following operation modes can be specified in 1-bit units. (1) Port mode In this port mode, P80 to P87 function as an 8-bit I/O port. These pins can be set to input or output mode in 1-bit units by using port mode register 8 (PM8). When used as an input port pins, an on-chip pull-up resistor can be used by setting pull-up resistor option register 2 (PU2). (2) Control mode In this mode, P80 to P87 function as segment signal output pins (S20 to S27) for the LCD controller/driver. 2.2.7 P90 to P93 (Port 9) These pins constitute a 4-bit I/O port. controller/driver segment signal. The following operation modes can be specified in 1-bit units. (1) Port mode In this mode, P90 to P93 function as a 4-bit I/O port. These pins can be set to input or output mode in 1-bit units by using port mode register 9 (PM9). When used as input port pins, an on-chip pull-up resistor can be used by setting pull-up resistor option register 2 (PU2). (2) Control mode In this mode, P90 to P93 function as segment signal output pins (S16 to S19) for the LCD controller/driver. 2.2.8 S0 to S15 These pins are segment signal output pins for the LCD controller/driver. 2.2.9 COM0 to COM3 These pins are common signal output pins for the LCD controller/driver. 2.2.10 VLC0 to VLC2 These pins are power supply voltage pins to drive the LCD. 2.2.11 BIAS This pin supplies power to drive the LCD. 2.2.12 AVREF This pin is the A/D converter reference voltage pin. Connect it to VDD0, VDD1, VSS0, or VSS1 when not using the A/D converter. 2.2.13 AVDD This pin is the A/D converter analog circuit power supply pin. Always keep it at the same potential as the VDD0 pin (even when the A/D converter is not used). In addition to I/O port pins, these pins can also function as LCD In addition to I/O port pins, these pins can also function as LCD
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2.2.14 AVSS This pin is the A/D converter ground potential pin. Always keep it at the same potential as the VSS0 pin (even when the A/D converter is not used). 2.2.15 RESET This pin inputs an active-low system reset signal. 2.2.16 X1, X2 These pins are used to connect a crystal resonator for main system clock oscillation. To supply an external clock, input the clock to X1 and input the inverted signal to X2. 2.2.17 XT1, XT2 These pins are used to connect a crystal resonator for subsystem clock oscillation. To supply an external clock, input the clock to XT1 and input the inverted signal to XT2. 2.2.18 VDD0, VDD1 VDD0 is the positive power supply pin for ports, while VDD1 is the positive power supply pin for other than ports. 2.2.19 VSS0, VSS1 VSS0 is the ground potential pin for ports, while the VSS1 is the ground potential pin for other than ports. 2.2.20 VPP (PD78F9418A only) A high voltage should be applied to this pin when the flash memory programming mode is set and when the program is written or verified. Handle the pins in either of the following ways. * Independently connect a 10 k pull-down resistor. * Switch this pin to be directly connected to the dedicated flash programmer in programming mode or to VSS0 or VSS1 in normal operation mode using a jumper on the board. If the wiring between the VPP pin and VSS0 or VSS1 pin is long, or external noise is superimposed on the VPP pin, the user program may not run correctly.
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2.2.21 IC (mask ROM version only) The IC (internally connected) pin is used to set the PD789407A and PD789417A Subseries in the test mode before shipment. In the normal operation mode, directly connect this pin to the VSS0 or VSS1 pin with as short a wiring length as possible. If a potential difference is generated between the IC pin and VSS0 or VSS1 pin due to a long wiring length between these pin, or due to external noise superimposed on the IC pin, the user program may not run correctly. * Directly connect the IC pin to the VSS0 or VSS1 pin.
VSS0, VSS1 IC
Keep short
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2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 2-1. For the I/O circuit configuration of each type, see Figure 2-1. Table 2-1. Types of Pin I/O Circuits
Pin Name I/O Circuit Type 5-H 8-C I/O Recommended Connection of Unused Pins
P00 to P03 P20/SCK/ASCK P21/SO/TxD P22/SI/RxD P23/CMPTOUT0/TO2 P24/INTP0/TI0 P25/INTP1/TI1 P26/INTP2/TO5 P27/INTP3/CPT5 P40/KR0 to P45/KR5 P46, P47 P50 to P53 (Mask ROM version) P50 to P53 (PD78F9418A) P60/ANI0/CMPIN0 P61/ANI1/CMPREF0 P62/ANI2 to P66/ANI6 P80/S27 to P87/S20 P90/S19 to P93/S16 S0 to S15 COM0 to COM3 VLC0 to VLC2 BIAS
I/O
Input: Independently connect to VDD0, VDD1, VSS0, or VSS1 via a resistor. Output: Leave open.
10-B 8-C Input: Independently connect to VSS0 or VSS1 via a resistor. Output: Leave open.
5-H 13-U
Input: Independently connect to VDD0, VDD1, VSS0, or VSS1 via a resistor. Output: Leave open. Input: Independently connect to VDD0 or VDD1 via a resistor. Output: Leave open.
13-T 9-D Input Connect directly to VDD0, VDD1, VSS0, or VSS1.
9-C 17-F I/O Input: Independently connect to VDD0, VDD1, VSS0, or VSS1 via a resistor. Output: Leave open. Leave open.
17-B 18-A -
Output
*-* Leave open. However, independently connect to VSS0 or VSS1 via a resistor when none of VLC0 to VLC2 are used. Connect directly to VDD0 or VDD1. Connect directly to VDD0, VDD1, VSS0, or VSS1. Connect directly to VSS0 or VSS1. Input - Connect directly to VSS0 or VSS1. Leave open. - Connect directly to VSS0 or VSS1. Independently connect to a 10 k pull-down resistor or connect directly to VSS0 or VSS1.
AVDD AVREF AVSS XT1 XT2 RESET IC (Mask ROM version) VPP (PD78F9418A) 2 -
Input *-*
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Figure 2-1. Pin I/O Circuits (1/2)
Type 2 Type 9-D
IN P-ch N-ch AVSS
+ -
IN
VREF (Threshold voltage)
Schmitt-triggered input with hysteresis characteristics
Input enable Comparator
Type 5-H
VDD0 Pull-up enable VDD0 Data P-ch IN/OUT Output disable N-ch VSS0
Type 10-B
VDD0
P-ch
Pull-up enable VDD0 Data P-ch
P-ch
IN/OUT Open drain Output disable VSS0 N-ch
Input enable
Type 8-C
VDD0
Type 13-T
IN/OUT Data Output disable N-ch
Pull-up enable VDD0 Data P-ch
P-ch
VSS0
IN/OUT Output disable N-ch VSS0
Input enable Middle-voltage input buffer
Type 9-C
IN P-ch N-ch AVSS VREF (Threshold voltage) Comparator
+ -
Type 13-U
VDD0 Pull-up resistor (mask option) IN/OUT Output data Output disable
Input enable
N-ch
VSS0 Input enable Middle-voltage input buffer
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Figure 2-1. Pin I/O Circuits (2/2)
Type 17-B Type 17-F
VDD0
VLC0 VLC1 P-ch N-ch P-ch
Pull-up enable Data
P-ch VDD0 P-ch IN/OUT
SEG data P-ch N-ch N-ch
OUT
VLC2
Output disable
N-ch VSS0
VSS1
Input enable
Type 18-A
VLC0
VLC0 VLC1 P-ch N-ch P-ch N-ch P-ch N-ch N-ch P-ch OUT
P-ch VLC1 SEG data SEG output disable VLC2 N-ch
P-ch
COM data VLC2
N-ch
VSS1
VSS1
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3.1 Memory Space
The PD789407A and PD789417A Subseries can access 64 KB of memory space. Figures 3-1 through 3-4 show the memory maps. Figure 3-1. Memory Map (PD789405A and PD789415A)
FFFFH Special function registers 256 x 8 bits FF00H FEFFH Internal high-speed RAM 512 x 8 bits FD00H FCFFH
Reserved
FA1CH FA1BH Data memory space RAM space for LCD data 28 x 4 bits FA00H F9FFH
Reserved 2FFFH 3000H 2FFFH Program area
Program memory space
Internal ROM 12288 x 8 bits
0080H 007FH CALLT table area 0040H 003FH Program area 0024H 0023H
0000H
0000H
Vector table area
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Figure 3-2. Memory Map (PD789406A and PD789416A)
FFFFH Special function registers 256 x 8 bits FF00H FEFFH Internal high-speed RAM 512 x 8 bits FD00H FCFFH
Reserved
FA1CH FA1BH Data memory space RAM space for LCD data 28 x 4 bits FA00H F9FFH
Reserved 3FFFH 4000H 3FFFH Program area
Program memory space
Internal ROM 16384 x 8 bits
0080H 007FH CALLT table area 0040H 003FH Program area 0024H 0023H
0000H
0000H
Vector table area
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Figure 3-3. Memory Map (PD789407A and PD789417A)
FFFFH Special function registers 256 x 8 bits FF00H FEFFH Internal high-speed RAM 512 x 8 bits FD00H FCFFH
Reserved
FA1CH FA1BH Data memory space RAM space for LCD data 28 x 4 bits FA00H F9FFH
Reserved 5FFFH 6000H 5FFFH Program area
Program memory space
Internal ROM 24576 x 8 bits
0080H 007FH CALLT table area 0040H 003FH Program area 0024H 0023H
0000H
0000H
Vector table area
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Figure 3-4. Memory Map (PD78F9418A)
FFFFH Special function registers 256 x 8 bits FF00H FEFFH Internal high-speed RAM 512 x 8 bits FD00H FCFFH
Reserved
FA1CH FA1BH Data memory space RAM space for LCD data 28 x 4 bits FA00H F9FFH
Reserved 7FFFH 8000H 7FFFH Program area
Program memory space
Flash memory 32768 x 8 bits
0080H 007FH CALLT table area 0040H 003FH Program area 0024H 0023H
0000H
0000H
Vector table area
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3.1.1 Internal program memory space The internal program memory space stores programs and table data. This space is usually addressed by the program counter (PC). The products in the PD789407A and PD789417A Subseries contain the following internal ROM (or flash memory) capacities. Table 3-1. Internal ROM Capacity
Part Number Structure Internal ROM Capacity 12288 x 8 bits 16384 x 8 bits 24576 x 8 bits Flash memory 32768 x 8 bits
PD789405A, 789415A PD789406A, 789416A PD789407A, 789417A PD78F9418A
Mask ROM
The following areas are allocated to the internal program memory space. (1) Vector table area The 36-byte area of addresses 0000H to 0023H is reserved as a vector table area. This area stores program start addresses to be used when branching by RESET input or interrupt request generation. Of a 16-bit program address, the lower 8 bits are stored in an even address, and the higher 8 bits are stored in an odd address. Table 3-2. Vector Table
Vector Table Address 0000H 0004H 0006H 0008H 000AH 000CH 000EH 0010H 0012H Interrupt Request RESET input INTWDT INTP0 INTP1 INTP2 INTP3 INTSR00/INTCSI00 INTST00 INTWT Vector Table Address 0014H 0016H 0018H 001AH 001CH 001EH 0020H 0022H Interrupt Request INTWTI INTTM00 INTTM01 INTTM02 INTTM50 INTKR00 INTAD0 INTCMP0
(2)
CALLT instruction table area The subroutine entry address of a 1-byte call instruction (CALLT) can be stored in the 64-byte area of addresses 0040H to 007FH.
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3.1.2 Internal data memory space The PD789407A and PD789417A Subseries products incorporate the following RAM: (1) Internal high-speed RAM An internal high-speed RAM is allocated to the area between FD00H and FEFFH. The internal high-speed RAM is also used as a stack. (2) LCD data RAM An LCD data RAM is allocated to the area between FA00H and FA1BH. The LCD display RAM can also be used as ordinary RAM. 3.1.3 Special function register (SFR) area Special function registers (SFRs) of on-chip peripheral hardware are allocated to the area of FF00H to FFFFH (see Table 3-3).
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3.1.4 Data memory addressing The PD789407A and PD789417A Subseries are provided with a variety of addressing modes to make memory manipulation as efficient as possible. In the area that holds data memory (FD00H to FFFFH) especially, specific modes of addressing that correspond to the particular function of an area, such as the special function registers (SFR) or general-purpose registers, are available. modes. Figure 3-5. Data Memory Addressing (PD789405A and PD789415A)
FFFFH Special function registers (SFR) 256 x 8 bits FF20H FF1FH FF00H FEFFH Short direct addressing SFR addressing
Figures 3-5 through 3-8 show the data memory addressing
Internal high-speed RAM 512 x 8 bits FE20H FE1FH FD00H FCFFH
Direct addressing Reserved Register indirect addressing FA1CH FA1BH RAM space for LCD data 28 x 4 bits FA00H F9FFH Based addressing
Reserved
3000H 2FFFH Internal ROM 12288 x 8 bits 0000H
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Figure 3-6. Data Memory Addressing (PD789406A and PD789416A)
FFFFH Special function registers (SFR) 256 x 8 bits FF20H FF1FH FF00H FEFFH Short direct addressing SFR addressing
Internal high-speed RAM 512 x 8 bits FE20H FE1FH FD00H FCFFH
Direct addressing Reserved Register indirect addressing Based addressing
FA1CH FA1BH RAM space for LCD data 28 x 4 bits FA00H F9FFH
Reserved
4000H 3FFFH Internal ROM 16384 x 8 bits 0000H
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Figure 3-7. Data Memory Addressing (PD789407A and PD789417A)
FFFFH Special function registers (SFR) 256 x 8 bits FF20H FF1FH FF00H FEFFH Short direct addressing SFR addressing
Internal high-speed RAM 512 x 8 bits FE20H FE1FH FD00H FCFFH
Direct addressing Reserved Register indirect addressing Based addressing RAM space for LCD data 28 x 4 bits FA00H F9FFH
FA1CH FA1BH
Reserved
6000H 5FFFH Internal ROM 24576 x 8 bits 0000H
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Figure 3-8. Data Memory Addressing (PD78F9418A)
FFFFH Special function registers (SFR) 256 x 8 bits FF20H FF1FH FF00H FEFFH Short direct addressing SFR addressing
Internal high-speed RAM 512 x 8 bits FE20H FE1FH FD00H FCFFH
Direct addressing Reserved Register indirect addressing Based addressing RAM space for LCD data 28 x 4 bits FA00H F9FFH
FA1CH FA1BH
Reserved
8000H 7FFFH Flash memory 32768 x 8 bits 0000H
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3.2 Processor Registers
The PD789407A and PD789417A Subseries are provided with the following on-chip processor registers. 3.2.1 Control registers The control registers contains special functions to control the program sequence statuses and stack memory. A program counter, a program status word, and a stack pointer constitute the control registers. (1) Program counter (PC) The program counter is a 16-bit register that holds the address information of the next program to be executed. In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instruction is executed, immediate data or register contents are set. RESET input sets the program counter to the reset vector table values at addresses 0000H and 0001H. Figure 3-9. Program Counter Configuration
15 PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 0 PC0
(2)
Program status word (PSW) The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are automatically restored upon execution of the RETI and POP PSW instructions. RESET input sets the PSW to 02H. Figure 3-10. Program Status Word Configuration
7 IE Z 0 AC 0 0 1 0 CY
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(a)
Interrupt enable flag (IE) This flag controls the interrupt request acknowledgment operations of the CPU. When 0, IE is set to the interrupt disable status (DI), and all interrupt requests other than non-maskable interrupts are disabled. When 1, IE is set to the interrupt enable status (EI). At this time, interrupt request acknowledgment is controlled by an interrupt mask flag corresponding to the interrupt source. IE is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI instruction execution.
(b)
Zero flag (Z) When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.
(c)
Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases.
(d)
Carry flag (CY) This flag stores an overflow or underflow upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution.
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(3)
Stack pointer (SP) This is a 16-bit register used to hold the start address of the memory stack area. Only the internal highspeed RAM area can be set as the stack area. Figure 3-11. Stack Pointer Configuration
15 0 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
SP SP15 SP14 SP13 SP12 SP11 SP10
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restore) from the stack memory. Each stack operation saves/restores data as shown in Figures 3-12 and 3-13. Caution Since RESET input makes the SP contents undefined, be sure to initialize the SP before instruction execution. Figure 3-12. Data Saved to Stack Memory
PUSH rp instruction CALL, CALLT instructions SP SP SP _ 2 SP _ 2 SP _ 1 SP Lower register pairs Higher register pairs SP SP _ 2 SP _ 2 SP _ 1 SP PC7 to PC0 PC15 to PC8 SP _ 3 SP _ 3 SP _ 2 SP _ 1 SP PC7 to PC0 PC15 to PC8 PSW Interrupt
Figure 3-13. Data Restored from Stack Memory
POP rp instruction RET instruction RETI instruction
SP SP + 1 SP SP + 2
Lower register pairs Higher register pairs SP
SP SP + 1 SP + 2
PC7 to PC0 PC15 to PC8
SP SP + 1 SP + 2 SP SP + 3
PC7 to PC0 PC15 to PC8 PSW
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3.2.2 General-purpose registers The general-purpose registers consist of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, and two 8-bit registers can be used in pairs as a 16-bit register (AX, BC, DE, and HL). General-purpose registers can be described in terms of functional names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute names (R0 to R7 and RP0 to RP3). Figure 3-14. General-Purpose Register Configuration (a) Absolute names
16-bit processing 8-bit processing R7 RP3 R6 R5 RP2 R4 R3 RP1 R2 R1 RP0 R0 15 0 7 0
(b) Functional names
16-bit processing 8-bit processing H HL L D DE E B BC C A AX X 15 0 7 0
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3.2.3 Special function registers (SFR) Unlike a general-purpose register, each special function register has a special function. SFRs are allocated in the 256-byte area FF00H to FFFFH. A special function register can be manipulated, like a general-purpose register, using operation, transfer, and bit manipulation instructions. The manipulatable bit unit (1, 8, or 16) differs depending on the special function register type. Each manipulation bit unit can be specified as follows. * 1-bit manipulation Describes a symbol reserved by assembler for the 1-bit manipulation instruction operand (sfr.bit). manipulation can also be specified by an address. * 8-bit manipulation Describes a symbol reserved by assembler for the 8-bit manipulation instruction operand (sfr). manipulation can also be specified by an address. * 16-bit manipulation Describes a symbol reserved by assembler for the 16-bit manipulation instruction operand. When addressing an address, describe an even address. Table 3-3 lists the special function registers. The meanings of the symbols in this table are as follows: * Symbol Indicates the address of the special function register. The symbols shown in this column are reserved words in the assembler, and have been defined in the header file named "sfrbit.h" in the C compiler. Therefore, these symbols can be used as instruction operands if an assembler or integrated debugger is used. * R/W Indicates whether the special function register in question can be read or written. R/W: Read/write R: W: Read only Write only This This
* Manipulatable bit unit Indicates the bit units (1, 8, 16) in which the special function register in question can be manipulated. * After reset Indicates the status of the special function register when the RESET signal is input.
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Table 3-3. Special Function Register List (1/2)
Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit 1 Bit FF00H FF02H FF04H FF05H FF06H FF08H FF09H FF10H Port 0 Port 2 Port 4 Port 5 Port 6 Port 8 Port 9 Transmit shift register 00 Receive buffer register 00 FF14H FF15H FF16H FF17H FF18H FF19H FF1AH FF1BH FF20H FF22H FF24H FF25H FF28H FF29H FF42H FF48H FF4AH FF4EH Port mode register 0 Port mode register 2 Port mode register 4 Port mode register 5 Port mode register 8 Port mode register 9 Timer clock selection register 2 16-bit timer mode control register 50 Watch timer mode control register Comparator mode register 0 16-bit capture register 50 16-bit timer counter 50 16-bit compare register 50 CR50L CR50H TM50L TM50H TCP50L TCP50 TCP50H PM0 PM2 PM4 PM5 PM8 PM9 TCL2 TMC50 WTM CMPRM0 R/W - - - - - - - - - - - 00H FFH - - Notes 2, 3 Undefined TM50 R - - Notes 2, 3 0000H CR50 W - - Notes 2, 3 FFFFH A/D conversion result register 0 P0 P2 P4 P5 P6 P8 P9 TXS00 SIO00 RXB00 ADCR0 W R R R/W R/W - - - 8 Bits
Note 1
After Reset
16 Bits - - - - - - - - -
Note 2
00H
FFH Undefined
Notes 1. If the A/D conversion result register is used for the 8-bit A/D converter (PD789407A Subseries), it can be accessed only in 8-bit units. In this case, it is considered to have been mapped at address FF15H. If the register is used for the 10-bit A/D converter (PD789417A Subseries), it can be accessed only in 16-bit units. If the PD78F9418A is used as the flash memory version of the PD789405A,
PD789406A, or PD789407A, 8-bit access is also possible, provided that the object file has been
assembled using the PD789405A, PD789406A, or PD789407A. 2. 16-bit access is possible only in short direct addressing. 3. Although CR50, TM50, and TCP50 are 16-bit access dedicated registers, an 8-bit access is also possible. When performing an 8-bit access, use direct addressing.
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Table 3-3. Special Function Register List (2/2)
Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit 1 Bit FF50H FF51H FF53H FF54H FF55H FF57H FF58H FF59H FF5BH FF70H 8-bit compare register 00 8-bit timer counter 00 8-bit timer mode control register 00 8-bit compare register 01 8-bit timer counter 01 8-bit timer mode control register 01 8-bit compare register 02 8-bit timer counter 02 8-bit timer mode control register 02 Asynchronous serial interface mode register 00 Asynchronous serial interface status register 00 Serial operation mode register 00 Baud rate generator control register 00 A/D converter mode register 0 A/D input selection register 0 LCD display mode register 0 LCD port selector 0 LCD clock control register 0 Interrupt request flag register 0 Interrupt request flag register 1 Interrupt mask flag register 0 Interrupt mask flag register 1 External interrupt mode register 0 External interrupt mode register 1 Suboscillation mode register Subclock control register Pull-up resistor option register 1 Pull-up resistor option register 2 Key return mode register 00 Pull-up resistor option register 0 Watchdog timer mode register Oscillation stabilization time selection register Processor clock control register CR00 TM00 TMC00 CR01 TM01 TMC01 CR02 TM02 TMC02 ASIM00 W R R/W W R R/W W R R/W - - - - - - R - - - - 8 Bits 16 Bits - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 04H 00H FFH Undefined 00H Undefined 00H Undefined 00H After Reset
FF71H
ASIS00
FF72H FF73H FF80H FF84H FFB0H FFB1H FFB2H FFE0H FFE1H FFE4H FFE5H FFECH FFEDH FFF0H FFF2H FFF3H FFF4H FFF5H FFF7H FFF9H FFFAH
CSIM00 BRGC00 ADM0 ADS0 LCDM0 LPS0 LCDC0 IF0 IF1 MK0 MK1 INTM0 INTM1 SCKM CSS PU1 PU2 KRM00 PU0 WDTM OSTS
R/W
FFFBH
PCC
02H
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3.3 Instruction Address Addressing
An instruction address is determined by program counter (PC) contents. PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. When a branch instruction is executed, the branch destination information is set to the PC and branched by the following addressing (for details of each instruction, refer to the 78K/0S Series Instructions User's Manual (U11047E)). 3.3.1 Relative addressing [Function] The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (PC) and branched. The displacement value is treated as signed two's complement data (-128 to +127) and bit 7 becomes a sign bit. This means that information is relatively branched to a location between -128 and +127, from the start address of the next instruction when relative addressing is used. This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed. [Illustration]
15 PC + 15 8 7 S jdisp8 15 PC When S = 0, indicates all bits 0. When S = 1, indicates all bits 1. 0 6 0 0 ... PC is the start address of the next instruction of a BR instruction.
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3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 instruction is executed. The CALL !addr16 and BR !addr16 instructions can be branched to any location in the memory space. [Illustration] In case of CALL !addr16 and BR !addr16 instructions
7 CALL or BR Low addr. High addr. 0
15 PC
87
0
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3.3.3 Table indirect addressing [Function] The table contents (branch destination address) of the particular location to be addressed by the lower 5-bit immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and branched. This function is carried out when the CALLT [addr5] instruction is executed. The instruction enables a branch to any location in the memory space by referring to the addresses stored in the memory table at 40H to 7FH. [Illustration]
7 Instruction code 0 6 1 5 ta4-0 1 0 0
15 Effective address 0 0 0 0 0 0 0
8 0
7 0
6 1
5
10 0
7
Memory (table) Low addr.
0
Effective address + 1
High addr.
15 PC
8
7
0
3.3.4 Register addressing [Function] The register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration]
7 rp A 0 7 X 0
15 PC
8
7
0
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3.4 Operand Address Addressing
The following methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 Direct addressing [Function] The memory indicated with immediate data in an instruction word is directly addressed. [Operand format]
Identifier addr16 Label or 16-bit immediate data Description
[Description example] MOV A, !FE00H; When setting !addr16 to FE00H
Instruction code 0 0 1 0 1 0 0 1 Opcode
0
0
0
0
0
0
0
0
00H
1
1
1
1
1
1
1
0
FEH
[Illustration]
7 Opcode

0
addr16 (low) addr16 (high) Memory
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3.4.2 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space is the 256-byte space FE20H to FF1FH where the addressing is applied. An internal highspeed RAM and special function registers (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively. The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the whole SFR area. Ports that are frequently accessed in a program and a compare register of the timer/event counter are mapped in this area, and these SFRs can be manipulated with a small number of bytes and clocks. When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH, bit 8 is set to 1. See [Illustration] below. [Operand format]
Identifier saddr saddrp Description Label or FE20H to FF1FH immediate data Label or FE20H to FF1FH immediate data (even address only)
[Description example] MOV FE30H, #50H; When setting saddr to FE30H and the immediate data to 50H
Instruction code 1 1 1 1 0 1 0 1 Opcode
0
0
1
1
0
0
0
0
30H (saddr-offset)
0
1
0
1
0
0
0
0
50H (Immediate data)
[Illustration]
7 Opcode saddr-offset 0
Short direct memory 15 Effective address 1 1 1 1 1 1 1 8 0
When 8-bit immediate data is 20H to FFH, = 0. When 8-bit immediate data is 00H to 1FH, = 1.
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3.4.3 Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can be accessed using short direct addressing. [Operand format]
Identifier sfr Special function register name Description
[Description example] MOV PM0, A; When selecting PM0 for sfr
Instruction code 1 1 1 0 0 1 1 1
0
0
1
0
0
0
0
0
[Illustration]
7 Opcode sfr-offset 0
SFR 15 Effective Address 1 1 1 1 1 1 1 87 1 0
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3.4.4 Register addressing [Function] In the register addressing mode, general-purpose registers are accessed as operands. The general-purpose register to be accessed is specified by the register specification code or functional name in the instruction code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code. [Operand format]
Identifier r rp X, A, C, B, E, D, L, H AX, BC, DE, HL Description
r and rp can be described using absolute names (R0 to R7 and RP0 to RP3) as well as functional names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL). [Description example] MOV A, C; When selecting the C register for r
Instruction code 0 0 0 0 1 0 1 0
0
0
1
0
0
1
0
1
Register specification code
INCW DE; When selecting the DE register pair for rp
Instruction code 1 0 0 0 1 0 0 0 Register specification code
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3.4.5 Register indirect addressing [Function] In the register indirect addressing mode, memory is manipulated according to the contents of a register pair specified as an operand. The register pair to be accessed is specified by the register pair specification code in an instruction code. This addressing can be carried out for all the memory spaces. [Operand format]
Identifier - [DE], [HL] Description
[Description example] MOV A, [DE]; When selecting register pair [DE]
Instruction code 0 0 1 0 1 0 1 1
[Illustration]
15 DE D 7 Addressed memory contents are transferred. 7 A 0 87 E 0 Memory address specified with register pair DE. 0
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3.4.6 Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces. [Operand format]
Identifier - [HL+byte] Description
[Description example] MOV A, [HL+10H]; When setting byte to 10H
Instruction code 0 0 1 0 1 1 0 1
0
0
0
1
0
0
0
0
3.4.7 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is saved/restored upon generation of an interrupt request. Stack addressing can only be used to access the internal high-speed RAM area. [Description example] In the case of PUSH DE
Instruction code 1 0 1 0 1 0 1 0
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4.1 Function of Port
The PD789407A and PD789417A Subseries are provided with the ports shown in Figure 4-1, enabling various methods of control. Numerous other functions are provided that can be used in addition to the digital I/O port function. For more information on these additional functions, see CHAPTER 2 PIN FUNCTIONS. Figure 4-1. Port Types
Port 5
P50
P00
P53
P03
Port 0
Port 6
P60
P20
P66 P27
Port 2
Port 8 Port 9
P80
P40
P87 P90
P47
Port 4
P93
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Table 4-1. Port Functions
Pin Name P00 to P03 I/O I/O Function Port 0. 4-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, use of an on-chip pull-up resistor can be specified by setting pull-up resistor option register 0 (PU0). Port 2. 8-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, use of an on-chip pull-up resistor can be specified by setting pull-up resistor option register 1 (PU1). After Reset Input Alternate Function -
P20 P21 P22 P23 P24 P25 P26 P27 P40 to P45
I/O
Input
SCK/ASCK SO/TxD SI/RxD CMPTOUT0/TO2 INTP0/TI0 INTP1/TI1 INTP2/TO5 INTP3/CPT5
I/O
P46, P47
Port 4. 8-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, use of an on-chip pull-up resistor can be specified by setting pull-up resistor option register 0 (PU0). Port 5. 4-bit N-ch open-drain I/O port. Input/output can be specified in 1-bit units. For a mask ROM version, use of an on-chip pull-up resistor can be specified by the mask option. Port 6. 7-bit input port.
Input
KR0 to KR5
-
P50 to P53
I/O
Input
-
P60 P61 P62 to P66 P80 to P87
Input
Input
ANI0/CMPIN0 ANI1/CMPREF0 ANI2 to ANI6
I/O
Port 8. 8-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, use of an on-chip pull-up resistor can be specified by setting pull-up resistor option register 2 (PU2). Port 9. 4-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, use of an on-chip pull-up resistor can be specified by setting pull-up resistor option register 2 (PU2).
Input
S27 to S20
P90 to P93
I/O
Input
S19 to S16
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4.2 Configuration of Ports
The ports consist of the following hardware. Table 4-2. Configuration of Port
Item Control registers Configuration Port mode registers (PMm: m = 0, 2, 4, 5, 8, 9) Pull-up resistor option registers (PUm: m = 0 to 2) Total: 43 (input: 7, I/O: 36) * Mask ROM version Total: 36 (software control: 32, mask option control: 4) * Flash memory version Total: 32 (software control only)
Ports Pull-up resistors
4.2.1 Port 0 This is a 4-bit I/O port with an output latch. Port 0 can be specified as input or output in 1-bit units by using port mode register 0 (PM0). When the P00 to P03 pins are used as input port pins, on-chip pull-up resistors can be connected in 4-bit units by setting pull-up resistor option register 0 (PU0). Port 0 is set to input mode when the RESET signal is input. Figure 4-2 shows a block diagram of port 0. Figure 4-2. Block Diagram of P00 to P03
VDD0 WRPU0
PU00 RD
P-ch
Internal bus
WRPORT Output latch (P00 to P03) WRPM
Selector
P00 to P03
PM00 to PM03
PU0: Pull-up resistor option register 0 PM: RD: WR: Port mode register Port 0 read signal Port 0 write signal
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4.2.2 Port 2 This is an 8-bit I/O port with an output latch. Port 2 can be specified as input or output in 1-bit units by using port mode register 2 (PM2). When using the P20 to P27 pins as input port pins, on-chip pull-up resistors can be connected in 1-bit units by setting pull-up resistor option register 1 (PU1). Port 2 is also used as a data I/O and clock I/O to and from the serial interface, timer I/O, and external interrupt. Port 2 is set to input mode when the RESET signal is input. Figures 4-3 through 4-7 show block diagrams of port 2. Caution When using the pins of port 2 for the serial interface, the I/O or output latch must be set according to the function to be used. For how to set the latches, see Table 13-2 Operation Mode Settings of Serial Interface 00. Figure 4-3. Block Diagram of P20
VDD0 WRPU1
PU120
P-ch
Alternate function RD
Internal bus
WRPORT Output latch (P20) WRPM
Selector
P20/ASCK/ SCK
PM20
Alternate function
PU1: Pull-up resistor option register 1 PM: RD: WR: Port mode register Port 2 read signal Port 2 write signal
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Figure 4-4. Block Diagram of P21
VDD0 WRPU1
PU121
P-ch
RD
Internal bus
WRPORT Output latch (P21) WRPM
Selector
P21/TxD/ SO
PM21
Alternate function
PU1: Pull-up resistor option register 1 PM: RD: WR: Port mode register Port 2 read signal Port 2 write signal
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Figure 4-5. Block Diagram of P22 and P24
VDD0 WRPU1
PU122, PU124
P-ch
Alternate function RD
Internal bus
WRPORT Output latch (P22, P24) WRPM
Selector
P22/RxD/SI P24/INTP0/TI0
PM22, PM24
PU1: Pull-up resistor option register 1 PM: RD: WR: Port mode register Port 2 read signal Port 2 write signal
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Figure 4-6. Block Diagram of P23
VDD0
WRPU1 PU123 RD
Selector
P-ch
Internal bus
VDD0 WRPORT Output latch (P23) OPDR P-ch
P23/TO2 /CMPTOUT0
WRPM PM23
N-ch
Alternate function Alternate function
OPDR: Bit 1 of comparator mode register 0, selection of N-ch open-drain output PU1: PM: RD: WR: Pull-up resistor option register 1 Port mode register Port 2 read signal Port 2 write signal
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Figure 4-7. Block Diagram of P25 to P27
VDD0 WRPU1
PU125 to PU127
P-ch
Alternate function RD
Selector
Internal bus
WRPORT Output latch (P25 to P27) WRPM
P25/INTP1/TI1 P26/INTP2/TO5 P27/INTP3/CPT5
PM25 to PM27
Alternate function
PU1: Pull-up resistor option register 1 PM: RD: WR: Port mode register Port 2 read signal Port 2 write signal
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4.2.3 Port 4 This is an 8-bit I/O port with an output latch. Port 4 can be specified as input or output in 1-bit units by using port mode register 4 (PM4). When using the P40 to P47 pins as input port pins, on-chip pull-up resistors can be connected in 8-bit units by setting pull-up resistor option register 0 (PU0). Port 4 is also used as a key return input. Port 4 is set to input mode when the RESET signal is input. Figures 4-8 and 4-9 show block diagrams of port 4. Caution When using the pins of port 4 as the key return, the key return mode register must be set according to the function to be used. For how to set the registers, see 15.3 (6) Key return mode register 00 (KRM00). Figure 4-8. Block Diagram of P40 to P45
VDD0 WRPU0
PU04 RD P-ch
WRKRM KRM000 to KRM005 WRPORT Output latch (P40 to P45) WRPM
Internal bus
Selector
P40/KR0 to P45/KR5
PM40 to PM45
Alternate function
KRM00: PU0: PM: RD: WR:
Key return mode register 00 Pull-up resistor option register 0 Port mode register Port 4 read signal Port 4 write signal
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Figure 4-9. Block Diagram of P46 and P47
VDD0 WRPU0
PU04 RD
P-ch
Internal bus
WRPORT Output latch (P46, P47) WRPM
Selector
P46, P47
PM46, PM47
PU0: Pull-up resistor option register 0 PM: RD: WR: Port mode register Port 4 read signal Port 4 write signal
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4.2.4 Port 5 This is a 4-bit N-ch open-drain I/O port with an output latch. Port 5 can be specified as input or output in 1-bit units by using port mode register 5 (PM5). For a mask ROM version, whether a pull-up resistor is to be incorporated can be specified by a mask option. Port 5 is set to input mode when the RESET signal is input. Figure 4-10 shows a block diagram of port 5. Figure 4-10. Block Diagram of P50 to P53
RD VDD0
Internal bus
Selector
Mask option resistor Mask ROM version only. For the flash memory version, a pull-up resistor is not incorporated.
WRPORT Output latch (P50 to P53) N-ch
P50 to P53
WRPM
PM50 to PM53
PM: RD: WR:
Port mode register Port 5 read signal Port 5 write signal
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CHAPTER 4 PORT FUNCTIONS
4.2.5 Port 6 This is a 7-bit input port. Port 6 is also used as an analog input to the A/D converter or comparator input. Port 6 is set to input mode when the RESET signal is input. Figures 4-11 and 4-12 show block diagrams of port 6. Figure 4-11. Block Diagram of P60 and P61
RD
Internal bus
+
A/D converter
P60/ANI0/CMPIN0 P61/ANI1/CMPREF0
-
VREF Comparator
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Figure 4-12. Block Diagram of P62 to P66
RD
Internal bus
+ A/D converter -
P62/ANI2 to P66/ANI6
VREF
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4.2.6 Port 8 This is an 8-bit I/O port with an output latch. Port 8 can be specified as input or output in 1-bit units by using port mode register 8 (PM8). When using the P80 to P87 pins as input port pins, internal pull-up resistors can be connected in 2-bit units by using pull-up resistor option register 2 (PU2). Port 8 is also used to output segment signals for the LCD controller/driver. Port 8 is set to input mode when the RESET signal is input. Figure 4-13 shows a block diagram of port 8. Figure 4-13. Block Diagram of P80 to P87
VDD0 WRPU2
PU28n
P-ch
RD
WRPORT
Internal bus
Output latch (P8m)
WRPM PM8m WRLPS LPS0
Selector
P80/S27 to P87/S20
Segment output
PU2: PM: RD: WR: LPS0:
Pull-up resistor option register 2 Port mode register Port 8 read signal Port 8 write signal LCD port selector 0
n = 0, 2, 4, 6, m = 0 to 7
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4.2.7 Port 9 This is a 4-bit I/O port with an output latch. Port 9 can be specified as input or output in 1-bit units by using port mode register 9 (PM9). When using the P90 to P93 pins as input port pins, on-chip pull-up resistors can be connected in 2-bit units by using pull-up resistor option register 2 (PU2). Port 9 is also used to output segment signals for the LCD controller/driver. Port 9 is set to input mode when the RESET signal is input. Figure 4-14 shows a block diagram of port 9. Figure 4-14. Block Diagram of P90 to P93
VDD0 WRPU2
PU29n
P-ch
RD
WRPORT
Internal bus
Output latch (P9m)
WRPM PM9m WRLPS LPS0
Selector
P90/S19 to P93/S16
Segment output
PU2: PM: RD: WR: LPS0:
Pull-up resistor option register 2 Port mode register Port 9 read signal Port 9 write signal LCD port selector 0
n = 0, 2, m = 0 to 3
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4.3 Registers Controlling Ports
The following two registers control the ports. * Port mode registers (PM0, PM2, PM4, PM5, PM8, and PM9) * Pull-up resistor option registers (PU0 to PU2) (1) Port mode registers (PM0, PM2, PM4, PM5, PM8, and PM9) These registers are used to set port input/output in 1-bit units. The port mode registers are independently set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets these registers to FFH. When port pins are used as alternate-function pins, set the port mode register and output latch according to Table 4-3. Caution As port 2 has an alternate function as the external interrupt input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. When the output mode is used, therefore, the interrupt mask flag should be set to 1 beforehand. Table 4-3. Port Mode Register and Output Latch Settings When Using Alternate Functions
Pin Name Alternate Function Name P23 CMPTOUT0 TO2 P24 INTP0 TI0 P25 INTP1 TI1 P26 INTP2 TO5 P27 INTP3 CPT5 P40 to P45 P80 to P87 P90 to P93
Note
PMxx I/O
Pxx
Output Output Input Input Input Input Input Output Input Input Input Output Output
0 0 1 1 1 1 1 0 1 1 1 0 0
0 0 x x x x x 0 x x x 0 0
KR0 to KR5 S27 to S20 S19 to S16
Note Set key return mode register 00 (KRM00) to 1 when using the alternate function (see 15.3 (6) Key return mode register 00 (KRM00)). Caution When port 2 is used for the serial interface, the I/O or output latch must be set according to the function used. Interface 00. Remark x: PMxx: Pxx: Don't care Port mode register Port output latch
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Operation Mode Settings of Serial
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Figure 4-15. Format of Port Mode Register
Symbol PM0 7 1 6 1 5 1 4 1 3 2 1 0 Address FF20H After reset FFH R/W R/W
PM03 PM02 PM01 PM00
PM2
PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20
FF22H
FFH
R/W
PM4
PM47 PM46 PM45 PM44 PM43 PM42 PM41 PM40
FF24H
FFH
R/W
PM5
1
1
1
1
PM53 PM52 PM51 PM50
FF25H
FFH
R/W
PM8
PM87 PM86 PM85 PM84 PM83 PM82 PM81 PM80
FF28H
FFH
R/W
PM9
1
1
1
1
PM93 PM92 PM91 PM90
FF29H
FFH
R/W
PMmn
Pmn pin I/O mode selection m = 0, 5, 9: n = 0 to 3 m = 2, 4, 8: n = 0 to 7 Output mode (output buffer on) Input mode (output buffer off)
0 1
(2)
Pull-up resistor option registers (PU0 to PU2) The pull-up resistor option registers (PU0 to PU2) set whether an on-chip pull-up resistor is used on each port. On a port specified by PU0 to PU2 to use an on-chip pull-up resistor, the pull-up resistor can be internally used only for the bits set in the input mode. No on-chip pull-up resistors can be used for the bits set in the output mode regardless of the setting of PU0 to PU2. This also applies when using the pins for alternate functions. PU0 to PU2 are set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets PU0 to PU2 to 00H. Figure 4-16. Format of Pull-Up Resistor Option Register 0
Symbol PU0 7 0 6 0 5 0 <4> PU04 3 0 2 0 1 0 <0> PU00 Address FFF7H After reset 00H R/W R/W
PU0m
Pm on-chip pull-up resistor selectionNote (m = 0 or 4)
0 1
On-chip pull-up resistor not used On-chip pull-up resistor used
Note PU0 selects whether on-chip pull-up resistors are to be used in 8-bit units, except for port 0, for which onchip pull-up resistors can be used only for four bits (P00 to P03). Caution Bits 1, 2, 3, 5, 6, and 7 must be fixed to 0.
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Figure 4-17. Format of Pull-Up Resistor Option Register 1
Symbol PU1 <7> <6> <5> <4> <3> <2> <1> <0> Address FFF3H After reset 00H R/W R/W
PU127 PU126 PU125 PU124 PU123 PU122 PU121 PU120
PU12m
P2 on-chip pull-up resistor selectionNote (m = 0 to 7)
0 1
On-chip pull-up resistor not used On-chip pull-up resistor used
Note PU1 selects whether on-chip pull-up resistors are to be used in 1-bit units. Figure 4-18. Format of Pull-Up Resistor Option Register 2
Symbol PU2 7 0 6 0 <5> <4> <3> <2> <1> <0> Address FFF4H After reset 00H R/W R/W
PU292 PU290 PU286 PU284 PU282 PU280
PU2mn
Pm on-chip pull-up resistor selectionNote (m = 8 or 9; n = 0, 2, 4, or 6)
0 1
On-chip pull-up resistor not used On-chip pull-up resistor used
Note PU2 selects whether on-chip pull-up resistors are to be used in 2-bit units (bit n and bit n+1). Caution Bits 6 and 7 must be fixed to 0.
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4.4 Operation of Ports
The operation of a port differs depending on whether the port is set in the input or output mode, as described below. 4.4.1 Writing to I/O port (1) In output mode A value can be written to the output latch of a port by using a transfer instruction. The contents of the output latch can be output from the pins of the port. Once data is written to the output latch, it is retained until new data is written to the output latch. (2) In input mode A value can be written to the output latch by using a transfer instruction. However, the status of the port pin is not changed because the output buffer is off. Once data is written to the output latch, it is retained until new data is written to the output latch. Caution A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port. However, this instruction accesses the port in 8-bit units. When this instruction is executed to manipulate a bit of an I/O port, therefore, the contents of the output latch of the pin that is set in the input mode and not subject to manipulation become undefined. 4.4.2 Reading from I/O port (1) In output mode The contents of the output latch can be read by using a transfer instruction. The contents of the output latch are not changed. (2) In input mode The status of a pin can be read by using a transfer instruction. The contents of the output latch are not changed. 4.4.3 Arithmetic operation of I/O port (1) In output mode An arithmetic operation can be performed on the contents of the output latch. The result of the operation is written to the output latch. The contents of the output latch are output from the port pins. Once data is written to the output latch, it is retained until new data is written to the output latch. (2) In input mode The contents of the output latch become undefined. However, the status of the pin is not changed because the output buffer is off. Caution A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port. However, this instruction accesses the port in 8-bit units. When this instruction is executed to manipulate a bit of an I/O port, therefore, the contents of the output latch of the pin that is set in the input mode and not subject to manipulation become undefined.
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CHAPTER 5 CLOCK GENERATOR
5.1 Functions of Clock Generator
The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are used. * Main system clock oscillator This circuit oscillates at 1.0 to 5.0 MHz. Oscillation can be stopped by executing the STOP instruction or setting the processor clock control register (PCC). * Subsystem clock oscillator This circuit oscillates at 32.768 kHz. Oscillation can be stopped by the suboscillation mode register (SCKM).
5.2 Configuration of Clock Generator
The clock generator consists of the following hardware. Table 5-1. Configuration of Clock Generator
Item Control registers Processor clock control register (PCC) Suboscillation mode register (SCKM) Subclock control register (CSS) Main system clock oscillator Subsystem clock oscillator Configuration
Oscillators
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Figure 5-1. Block Diagram of Clock Generator
Internal bus
FRC SCC Suboscillation mode register (SCKM)
XT1 XT2
Subsystem clock oscillator
fXT Prescaler 1/2 fXT 2
Watch timer LCD controller/driver
Clock to peripheral hardware
X1 X2
fX 22
Selector
Main system clock oscillator
Prescaler fX Standby controller Wait controller CPU clock (fCPU)
STOP MCC PCC1 Processor clock control register (PCC) Internal bus CLS CSS0 Subclock control register (CSS)
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5.3 Registers Controlling Clock Generator
The clock generator is controlled by the following registers. * Processor clock control register (PCC) * Suboscillation mode register (SCKM) * Subclock control register (CSS) (1) Processor clock control register (PCC) PCC selects the CPU clock and sets the division ratio. PCC is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets PCC to 02H. Figure 5-2. Format of Processor Clock Control Register
Symbol PCC 7 MCC 6 0 5 0 4 0 3 0 2 0 1 PCC1 0 0 Address FFFBH After reset 02H R/W R/W
MCC 0 1 Operation enabled Operation disabled
Control of main system clock oscillator operation
CSS0 PCC1
Selection of CPU clock (fCPU)Note
Minimum instruction execution time: 2/fCPU fX = 5.0 MHz or fXT = 32.768 kHz operation
0 0 1 1
0 1 0 1
fX fX/22 fXT/2
0.4 s 1.6 s 122 s
Note The CPU clock is selected according to a combination of the PCC1 flag in the processor clock control register (PCC) and the CSS0 flag in the subclock control register (CSS). See 5.3 (3) Subclock control register (CSS). Cautions 1. Bits 0 and 2 to 6 must be fixed to 0. 2. The MCC bit can be set only when the subsystem clock has been selected as the CPU clock. Remarks 1. fX: Main system clock oscillation frequency
2. fXT: Subsystem clock oscillation frequency
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(2)
Suboscillation mode register (SCKM) SCKM selects whether a feedback resistor is used for the subsystem clock, and controls the oscillation of the clock. SCKM is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets SCKM to 00H. Figure 5-3. Format of Suboscillation Mode Register
Symbol SCKM
7 0
6 0
5 0
4 0
3 0
2 0
1 FRC
0 SCC
Address FFF0H
After reset 00H
R/W R/W
FRC 0 1 On-chip feedback resistor used On-chip feedback resistor not used
Feedback resistor selectionNote
SCC 0 1 Operation enabled Operation disabled
Control of subsystem clock oscillator operation
Note The feedback resistor is necessary to adjust the bias point of the oscillation waveform to close to the mid point of the supply voltage. Only when the subclock is not used, the power consumption in STOP mode can be further reduced by setting FRC = 1. Cautions 1. Bits 2 to 7 must be fixed to 0. 2. Do not set the SCC bit when an external clock pulse is input, because the XT2 pin is pulled up to VDD0 or VDD1.
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(3)
Subclock control register (CSS) CSS specifies whether the main system or subsystem clock oscillator is to be selected. It also specifies how the CPU clock operates. CSS is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSS to 00H. Figure 5-4. Format of Subclock Control Register
Symbol CSS
7 0
6 0
5
4
3 0
2 0
1 0
0 0
Address FFF2H
After reset 00H
R/W R/WNote
CLS CSS0
CLS 0 1
CPU clock operation status Operation based on the output of the divided main system clock Operation based on the subsystem clock
CSS0 0 1
Selection of main system or subsystem clock oscillator Divided output from the main system clock oscillator Output from the subsystem clock oscillator
Note Bit 5 is read only. Caution Bits 0, 1, 2, 3, 6, and 7 must be fixed to 0.
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5.4 System Clock Oscillators
5.4.1 Main system clock oscillator The main system clock oscillator is oscillated by a crystal or ceramic resonator (5.0 MHz TYP.) connected across the X1 and X2 pins. An external clock can also be input to the circuit. In this case, input the clock signal to the X1 pin, and input the inverted signal to the X2 pin. Figure 5-5 shows the external circuit of the main system clock oscillator. Figure 5-5. External Circuit of Main System Clock Oscillator (a) Crystal or ceramic oscillation
VSS0, VSS1 X1
External clock
(b) External clock
X1
X2 Crystal or ceramic resonator
X2
Caution
When using the main system or subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in Figures 5-5 and 5-6 to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS0 and VSS1. Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator.
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5.4.2 Subsystem clock oscillator The subsystem clock oscillator is oscillated by a crystal resonator (32.768 kHz TYP.) connected across the XT1 and XT2 pins. An external clock can also be input to the circuit. In this case, input the clock signal to the XT1 pin, and input the inverted signal to the XT2 pin. Figure 5-6 shows the external circuit of the subsystem clock oscillator. Figure 5-6. External Circuit of Subsystem Clock Oscillator (a) Crystal oscillation
VSS0,VSS1 XT1 32.768 kHz XT2
External clock
(b) External clock
XT1
XT2
Crystal resonator
Caution
When using the main system or subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in Figures 5-5 and 5-6 to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS0 and VSS1. Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. When using the subsystem clock oscillator, pay special attention because the subsystem clock oscillator has low amplification to minimize current consumption.
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5.4.3 Examples of incorrect resonator connection Figure 5-7 shows examples of incorrect resonator connection. Figure 5-7. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line
PORTn (n = 0, 2, 4, 5, 6, 8, 9)
VSS0, VSS1
X1
X2
VSS0, VSS1
X1
X2
(c) Wiring near high fluctuating current
(d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates)
VDD0, VDD1
VSS0, VSS1
Pmn
X1
X2
VSS0, VSS1
X1
X2
High current
A
B High current
C
Remark
When using the subsystem clock, read X1 and X2 as XT1 and XT2, respectively, and connect resistors to the XT2 side in series.
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Figure 5-7. Examples of Incorrect Resonator Connection (2/2) (e) Signal is fetched (f) Signal lines of main system clock and subsystem clock are parallel and close together
VSS0, VSS1
VSS0, VSS1
X2
X1
XT2
XT1
X1
X2
XT2 is wired parallel to X1.
Remark
When using the subsystem clock, read X1 and X2 as XT1 and XT2, respectively, and connect resistors to the XT2 side in series.
Caution
If the X1 wire is parallel with the XT2 wire, crosstalk noise may occur between X1 and XT2, resulting in a malfunction. To avoid this, do not place the X1 and XT2 wires in parallel.
5.4.4 Divider The divider divides the output of the main system clock oscillator (fX) to generate various clocks. 5.4.5 When no subsystem clock is used If a subsystem clock is not necessary, for example, for low-power consumption operation or clock operation, handle the XT1 and XT2 pins as follows: XT1: Connect directly to VSS0 or VSS1 XT2: Leave open In this case, however, a small current leaks via the on-chip feedback resistor in the subsystem clock oscillator when the main system clock is stopped. To avoid this, set bit 1 (FRC) of the suboscillation mode register (SCKM) so that the on-chip feedback resistor will not be used. Also in this case, handle the XT1 and XT2 pins as stated above.
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5.5 Operation of Clock Generator
The clock generator generates the following clocks and controls the operation modes of the CPU, such as the standby mode. * Main system clock * Subsystem clock * CPU clock fCPU fX fXT
* Clock to peripheral hardware The operation of the clock generator is determined by the processor clock control register (PCC), suboscillation mode register (SCKM), and subclock control register (CSS), as follows. (a) The slow mode (1.6 s at 5.0 MHz operation) of the main system clock is selected when the RESET signal is generated (PCC = 02H). While a low level is being input to the RESET pin, oscillation of the main system clock is stopped. (b) Three types of minimum instruction execution time (0.4 s and 1.6 s main system clock (at 5.0 MHz operation), 122 s subsystem clock (at 32.768 kHz operation)) can be selected by the PCC, SCKM, and CSS settings. (c) Two standby modes, STOP and HALT, can be used with the main system clock selected. In a system where no subsystem clock is used, setting bit 1 (FRC) of SCKM so that the on-chip feedback resistor cannot be used reduces current consumption in the STOP mode. In a system where a subsystem clock is used, setting bit 0 of SCKM to 1 can cause the subsystem clock to stop oscillation. (d) Bit 4 (CSS0) of CSS can be used to select the subsystem clock so that low current consumption operation is used (at 122 s, 32.768 kHz operation). (e) With the subsystem clock selected, it is possible to cause the main system clock to stop oscillating by setting bit 7 (MCC) of PCC. The HALT mode can be used, but the STOP mode cannot. (f) The clock pulse for the peripheral hardware is generated by dividing the frequency of the main system clock. The subsystem clock pulse is supplied to 8-bit timer 02, the watch timer, and the LCD controller/driver only. As a result, 8-bit timer 02 (when watch timer output is selected for the count clock when the subsystem clock is running) and the watch function can continue running even in the standby mode. The other hardware stops when the main system clock stops, because it runs based on the main system clock (except for external input clock pulses).
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5.6 Changing Setting of System Clock and CPU Clock
5.6.1 Time required for switching between system clock and CPU clock The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC) and bit 4 (CSS0) of the subclock control register (CSS). Actually, the specified clock is not selected immediately after the setting of PCC has been changed; the old clock is used for the duration of several instructions after that (see Table 5-2). Table 5-2. Maximum Time Required for Switching CPU Clock
Set Value Before Switching CSS0 PCC1 CSS0 0 0 0 PCC1 0 Set Value After Switching CSS0 0 4 clocks PCC1 1 CSS0 1 2fX/fXT clocks (306 clocks) fX/2fXT clocks (76 clocks) 2 clocks PCC1 x
1
2 clocks
1
x
2 clocks
Remarks 1. Two clocks is the minimum instruction execution time of the CPU clock before switching. 2. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz. 3. x: Don't care
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5.6.2 Switching between system clock and CPU clock The following figure illustrates how the CPU clock and system clock are switched. Figure 5-8. Switching Between System Clock and CPU Clock
VDD
RESET
Interrupt request signal
System clock CPU clock
fX Low-speed operation
fX High-speed operation
fXT Subsystem clock operation
fX High-speed operation
Wait (6.55 ms: at 5.0 MHz operation) Internal reset operation
<1> The CPU is reset when the RESET pin is made low on power application. Reset is released when the RESET pin is later made high, and the main system clock starts oscillating. At this time, the oscillation stabilization time (2 /fX) is automatically secured. After that, the CPU starts instruction execution at the low speed of the main system clock (1.6 s at 5.0 MHz operation). <2> After the time required for the VDD voltage to rise to the level at which the CPU can operate at the high speed has elapsed, bit 1 (PCC1) of the processor clock control register (PCC) and bit 4 (CSS0) of the subclock control register (CSS) are rewritten so that the high-speed operation can be selected. <3> A drop of the VDD voltage is detected by an interrupt request signal. The clock is switched to the subsystem clock (at this moment, the subsystem clock must be in the stable oscillation status). <4> Recovery of the VDD voltage is detected by an interrupt request signal. Bit 7 (MCC) of PCC is set to 0, and the main system clock starts oscillating. After the time required for the oscillation to stabilize has elapsed, PCC1 and CSS0 are rewritten so that high-speed operation can be selected again. Caution When the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock.
15
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CHAPTER 6 16-BIT TIMER 50
16-bit timer 50 references the free-running counter and provides functions such as timer interrupt and timer output. In addition, the count value can be captured by a trigger pin.
6.1 Function of 16-Bit Timer 50
16-bit timer 50 has the following functions. * Timer interrupt * Timer output * Count value capture (1) Timer interrupt An interrupt is generated when the count value and compare value match. (2) Timer output Timer output control is possible when the count value and compare value match. (3) Count value capture The count value of 16-bit timer counter 50 (TM50) is latched to the capture register in synchronization with the capture trigger and retained.
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6.2 Configuration of 16-Bit Timer 50
16-bit timer 50 consists of the following hardware. Table 6-1. Configuration of 16-Bit Timer 50
Item Timer counter Registers 16 bits x 1 (TM50) Compare register: 16 bits x 1 (CR50) Capture register: 16 bits x 1 (TCP50) 1 (TO5) 16-bit timer mode control register 50 (TMC50) Port mode register 2 (PM2) Configuration
Timer outputs Control registers
Figure 6-1. Block Diagram of 16-Bit Timer 50
Internal bus 16-bit timer mode control register 50 (TMC50) TOF50 CPT501 CPT500 TOC50 TCL501 TCL500 TOE50 P26 output latch PM26
16-bit compare register 50 (CR50) Match
Selector
F/F TOD50 16-bit timer mode control register 50
TO5/P26/ INTP2
INTTM50 fX fX/25 OVF
16-bit timer counter 50 (TM50)
CPT5/P27/ INTP3
Edge detector
16-bit capture register 50 (TCP50)
16-bit counter read buffer
Internal bus
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(1)
16-bit compare register 50 (CR50) This register compares the value set to CR50 with the count value of 16-bit timer counter 50 (TM50), and when they match, generates an interrupt request (INTTM50). CR50 is set using a 16-bit memory manipulation instruction. Values from 0000H to FFFFH can be set. RESET input sets CR50 to FFFFH. Cautions 1. Although this register is manipulated by a 16-bit memory manipulation instruction, an 8-bit memory manipulation instruction can also be used. When manipulated by an 8-bit memory manipulation instruction, the accessing method should be direct addressing. 2. When rewriting CR50 during a count operation, preset CR50 to interrupt disabled using interrupt mask flag register 1 (MK1). Also, set the timer output data to inversion disabled using 16-bit timer mode control register 50 (TMC50). If CR50 is rewritten while interrupts are enabled, an interrupt request may be generated at the time of the rewrite.
(2)
16-bit timer counter 50 (TM50) This is a 16-bit register that counts count pulses. TM50 is read using a 16-bit memory manipulation instruction. TM50 is in free-running mode during count clock input. RESET input sets TM50 to 0000H, after which it enters free-running mode again. Cautions 1. The count value after releasing stop becomes undefined because the count operation is executed during the oscillation stabilization time. 2. Although this register is manipulated by a 16-bit memory manipulation instruction, an 8-bit memory manipulation instruction can also be used. When manipulated by an 8-bit memory manipulation instruction, the accessing method should be direct addressing. 3. When manipulated by an 8-bit memory manipulation instruction, readout should be performed in order from lower byte to higher byte and must be in pairs.
(3)
16-bit capture register 50 (TCP50) This is a 16-bit register that captures the contents of 16-bit timer counter 50 (TM50). TCP50 is set using a 16-bit memory manipulation instruction. RESET input makes TCP50 undefined. Caution Although this register is manipulated by a 16-bit memory manipulation instruction, an 8-bit memory manipulation instruction can also be used. When manipulated by an 8-bit memory manipulation instruction, the accessing method should be direct addressing.
(4)
16-bit counter read buffer This buffer latches the counter value of 16-bit timer counter 50 (TM50) and retains the count value.
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6.3 Registers Controlling 16-Bit Timer 50
The following two registers are used to control 16-bit timer 50. * 16-bit timer mode control register 50 (TMC50) * Port mode register 2 (PM2) (1) 16-bit timer mode control register 50 (TMC50) 16-bit timer mode control register 50 (TMC50) controls the setting of the count clock, capture edge, etc. TMC50 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMC50 to 00H.
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CHAPTER 6 16-BIT TIMER 50
Figure 6-2. Format of 16-Bit Timer Mode Control Register 50
Symbol TMC50 7 <6> 5 4 3 2 1 <0> Address FF48H After reset 00H R/W R/W Note 1
TOD50 TOF50 CPT501 CPT500 TOC50 TCL501 TCL500 TOE50
TOD50 0 1 Timer output is "0" Timer output is "1"
Timer output data
TOF50 0 1 Clear by reset and software Set by overflow of 16-bit timer
Overflow flag set
CPT501 CPT500 0 0 1 1 0 1 0 1 Capture operation disabled Rising edge of CPT5 Falling edge of CPT5 Both edges of CPT5
Capture edge selection
TOC50 0 1 Inverse disabled Inverse enabled
Timer output data inverse control
TCL501 TCL500 0 0 0 1 fX (5.0 MHz) Note 2 fX/25 (156.3 kHz) Note 3 Setting prohibited
16-bit timer 50 count clock selection
Other than above
TOE50 0 1 Output disabled (port mode) Output enabled
16-bit timer 50 output control
Notes 1. Bit 7 is read-only. 2. If the count clock is set to fX (TCL501 = 0, TCL500 = 0), the capture function cannot be used. When reading, set the CPU clock to the main system clock high-speed mode (PCC1 = 0, CSS0 = 0) (see Figure 5-2). 3. When reading, specify the main system clock as the CPU clock (PCC1 = 0, CSS0 = 0 or PCC1 = 1, CSS0 = 0) (see Figure 5-2). Remarks 1. fX: Main system clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz.
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(2)
Port mode register 2 (PM2) This register sets input/output of port 2 in 1-bit units. To use the P26/INTP2/TO5 pin for timer output, set PM26 and the output latch of P26 to 0. PM2 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM2 to FFH. Figure 6-3. Format of Port Mode Register 2
Symbol PM2
7
6
5
4
3
2
1
0
Address FF22H
After reset FFH
R/W R/W
PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20
PM26 0 1 Output mode (output buffer on) Input mode (output buffer off)
P26 pin I/O mode selection
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6.4 Operation of 16-Bit Timer 50
6.4.1 Operation as timer interrupt In the timer interrupt function, interrupts are repeatedly generated at the count value set to 16-bit compare register 50 (CR50) in advance at the interval set in TCL501 and TCL500. To operate the 16-bit timer as a timer interrupt, the following settings are required. * Set the count value to CR50 * Set 16-bit timer mode control register 50 (TMC50) as shown in Figure 6-4. Figure 6-4. Settings of 16-Bit Timer Mode Control Register 50 for Timer Interrupt Operation
TOD50 TOF50 CPT501 CPT500 TOC50 TCL501 TCL500 TOE50 TMC50 - 0/1 0/1 0/1 0/1 0 0/1 0/1 Setting of count clock (see Table 6-2)
Caution
If both the CPT501 flag and CPT500 flag are set to 0, the capture edge becomes operation prohibited.
When the count value of 16-bit timer counter 50 (TM50) matches the value set to CR50, counting of TM50 continues and an interrupt request signal (INTTM50) is generated. Table 6-2 shows the interval time, and Figure 6-5 shows the timing of the timer interrupt operation. Caution Be sure to process as follows when rewriting CR50 during a count operation. <1> Set interrupts to disabled (TMMK50 (bit 4 of interrupt mask flag register 1 (MK1)) = 1) <2> Set the inversion control of timer output data to disabled (TOC50 = 0) If CR50 is rewritten while interrupts are enabled, an interrupt request may be generated at the time of rewrite. Table 6-2. Interval Time of 16-Bit Timer 50
TCL501 0 0 Other than above TCL500 0 1 Count Clock 1/fX (0.2 s) 25/fX (6.4 s) Setting prohibited Interval Time 216/fX (13.1 ms) 221/fX (419.4 ms)
Remarks 1. fX: Main system clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz.
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Figure 6-5. Timing of Timer Interrupt Operation
t Count clock TM50 count value CR50 INTTM50 Interrupt acknowledged TO5 TOF50 Overflow flag set Interrupt acknowledged 0000H N 0001H N N FFFFH 0000H 0001H N N N FFFFH N
Remark
N = 0000H to FFFFH
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CHAPTER 6 16-BIT TIMER 50
6.4.2 Operation as timer output Timer outputs are repeatedly generated at the count value set to 16-bit compare register 50 (CR50) in advance at the interval set in TCL501 and TCL500. To operate 16-bit timer as a timer output, the following settings are required. * Set P26 to output mode (PM26 = 0) * Set the output latch of P26 to 0 * Set the count value to CR50 * Set 16-bit timer mode control register 50 (TMC50) as shown in Figure 6-6 Figure 6-6. Settings of 16-Bit Timer Mode Control Register 50 for Timer Output Operation
TOD50 TOF50 CPT501 CPT500 TOC50 TCL501 TCL500 TOE50 TMC50 - 0/1 0/1 0/1 1 0 0/1 1 TO5 output enable Setting of count clock (see Table 6-2) Inverse enable of timer output data
Caution
If both the CPT501 flag and CPT500 flag are set to 0, the capture edge becomes operation prohibited.
When the count value of 16-bit timer counter 50 (TM50) matches the value set in CR50, the output status of the TO5/INTP2/P26 pin is inverted. This enables timer output. At that time, TM50 counting continues and an interrupt request signal (INTTM50) is generated. Figure 6-7 shows the timing of timer output (see Table 6-2 for the interval time of 16-bit timer 50). Figure 6-7. Timer Output Timing
t Count clock TM50 count value CR50 INTTM50 Interrupt acknowledged TO5Note TOF50 Overflow flag set Interrupt acknowledged 0000H N 0001H N N FFFFH 0000H 0001H N N N FFFFH N
Note The TO5 initial value becomes low level when output is enabled (TOE50 = 1). Remark N = 0000H to FFFFH
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6.4.3 Capture operation In a capture operation, the count value of 16-bit timer counter 50 (TM50) is captured and latched to the capture register in synchronization with a capture trigger. Set as shown in Figure 6-8 to allow the 16-bit timer to start a capture operation. Figure 6-8. Settings of 16-Bit Timer Mode Control Register 50 for Capture Operation
TOD50 TOF50 CPT501 CPT500 TOC50 TCL501 TCL500 TOE50 TMC50 - 0/1 0/1 0/1 0/1 0 0/1 0/1 Count clock selection Capture edge selection (see Table 6-3)
16-bit capture register 50 (TCP50) starts a capture operation after the CPT5 capture trigger edge is defected, and latches and retains the count value of 16-bit timer counter 50 (TM50). TCP50 fetches the count value within 2 clocks and retains the count value until the next capture edge detection. Table 6-3 and Figure 6-9 shows the settings of the capture edge and the capture operation timing, respectively. Table 6-3. Settings of Capture Edge
CPT501 0 0 1 1 CPT500 0 1 0 1 Capture Edge Selection Capture operation prohibited CPT5 pin rising edge CPT5 pin falling edge CPT5 pin both edges
Caution
Because TCP50 is rewritten when a capture trigger edge is detected during TCP50 read, disable capture trigger edge detection during TCP50 read. Figure 6-9. Capture Operation Timing (Both Edges of CPT5 Pin Are Specified)
Count clock TM50 16-bit counter read buffer TCP50 0000H 0000H 0001H 0001H Undefined Capture start CPT5 Capture edge detection Capture edge detection N N N M-1 M M M Capture start
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6.4.4 16-bit timer counter 50 readout The count value of 16-bit timer counter 50 (TM50) is read out by a 16-bit manipulation instruction. TM50 readout is performed via a 16-bit counter read buffer. The 16-bit counter read buffer latches the TM50 count value, the buffer operation is held pending at the CPU clock falling edge after the read signal of the TM50 lower byte rises, and the count value is retained. The 16-bit counter read buffer value in the retention state can be read out as the count value. Cancellation of pending is performed at the CPU clock falling edge after the read signal of the TM50 higher byte falls. RESET input sets TM50 to 0000H and then to free-running mode again. Figure 6-10 shows the timing of 16-bit timer counter 50 readout. Cautions 1. The count value after releasing stop becomes undefined because the count operation is executed during the oscillation stabilization time. 2. AIthough TM50 is manipulated by a 16-bit transfer instruction, 8-bit transfer instruction can also be used. When using an 8-bit transfer instruction, execute by direct addressing. 3. When using an 8-bit transfer instruction, execute in order from lower byte to higher byte in pairs. If the only lower byte is read, the pending state of the 16-bit counter read buffer is not canceled, and if the only higher byte is read, an undefined count value is read. Figure 6-10. Readout Timing of 16-Bit Timer Counter 50
CPU clock Count clock TM50 16-bit counter read buffer TM50 read signal Read signal latch prohibited period 0000H 0000H 0001H 0001H N N N+1
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6.5 Cautions on Using 16-Bit Timer 50
6.5.1 Restrictions when rewriting 16-bit compare register 50 (1) Disable interrupts (TMMK50 = 1) and the inversion control of timer output (TOC50 = 0) before rewriting the compare register (CR50). If CR50 is rewritten with interrupts enabled, an interrupt request may be generated immediately. (2) Depending on the timing of rewriting the compare register (CR50), the interval time may become twice as long as the intended time. Similarly, a shorter waveform or twice-longer waveform than the intended timer output waveform may be output. To avoid this problem, rewrite the compare register using either of the following procedures. When rewriting using 8-bit access <1> Disable interrupts (TMMK50 = 1) and the inversion control of timer output (TOC50 = 0). <2> First rewrite the higher 1 byte of CR50 (16 bits). <3> Then rewrite the lower 1 byte of CR50 (16 bits). <4> Clear the interrupt request flag (TMIF50). <5> Enable timer interrupts/timer output inversion after half a cycle or more of the count clock has elapsed from the beginning of the interrupt. (count clock = 32/fX, CPU clock = fX) TM50_VCT: SET1 TMMK50 CLR1 TMC50.3 MOV MOV MOV MOV A,#xxH !0FF17H,A A,#yyH !0FF16H,A ; Disable timer interrupts (6 clocks) ; Disable timer output inversion (6 clocks) ; Set the rewrite value of higher byte (6 clocks) ; Rewrite CR50 higher byte (8 clocks) ; Set the rewrite value of lower byte (6 clocks) ; Rewrite CR50 lower byte (8 clocks) ; Clear interrupt request flag (6 clocks) ; Enable timer interrupts (6 clocks) ; Enable timer output inversion Total: 16 clocks or more
Note
CLR1 TMIF50 CLR1 TMMK50 SET1 TMC50.3
Note Because the INTTM50 signal becomes high level for half a cycle of the count clock after an interrupt is generated, the output is inverted if TOC50 is set to 1 during this period.
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When rewriting using 16-bit access <1> Disable interrupts (TMMK50 = 1) and the inversion control of timer output (TOC50 = 0). <2> Rewrite CR50 (16 bits). <3> Wait for one cycle or more of the count clock. <4> Clear the interrupt request flag (TMIF50). <5> Enable timer interrupts/timer output inversion. (count clock = 32/fX, CPU clock = fX) TM50_VCT SET1 TMMK50 CLR1 TMC50.3 MOVW AX,#xxyyH MOVW CR50,AX NOP NOP : NOP NOP CLR1 TMIF50 CLR1 TMMK50 SET1 TMC50.3 ; Clear interrupt request flag ; Enable timer interrupts ; Enable timer output inversion ; 16 NOP instructions (wait for 32/fX)
Note
; Disable timer interrupts ; Disable timer output inversion ; Set the rewrite value of CR50 ; Rewrite CR50
Note Clear the interrupt request flag (TMIF50) after waiting for one cycle or more of the count clock from the instruction rewriting CR50 (MOVW CR50, AX).
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 00 TO 02
7.1 Function of 8-Bit Timer/Event Counters 00 to 02
8-bit timer/event counters 00 to 02 have the following functions. * Interval timer (timer 00, timer 01, and timer 02) * External event counter (timer 00 and timer 01 only) * Square-wave output (timer 02 only) The PD789407A and PD789417A Subseries are provided with two 8-bit timer/event counter channels (timer 00 and timer 01) and one 8-bit timer channel (timer 02). When reading the description of timer 02, timer/event counter should be read as a timer. (1) 8-bit interval timer When the 8-bit timer/event counter is used as an interval timer, it generates an interrupt at an arbitrary time interval set in advance. Table 7-1. Interval Time of 8-Bit Timer/Event Counter 00
Minimum Interval Time 2 /fX (12.8 s)
6 14
Maximum Interval Time 2 /fX (3.28 ms) 2 /fX (26.2 ms)
17
Resolution 2 /fX (12.8 s)
6
2 /fX (102.4 s)
9
29/fX (102.4 s)
Remarks 1. fX: Main system clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz. Table 7-2. Interval Time of 8-Bit Timer/Event Counter 01
Minimum Interval Time 24/fX (3.2 s) 28/fX (51.2 s) Maximum Interval Time 212/fX (819.2 s) 216/fX (13.1 ms) 24/fX (3.2 s) 28/fX (51.2 s) Resolution
Remarks 1. fX: Main system clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz. Table 7-3. Interval Time of 8-Bit Timer 02
Minimum Interval Time 2 /fX (1.6 s)
3 11
Maximum Interval Time 2 /fX (409.6 s) 2 /fX (6.55 ms) 28/fXT (7.81 ms)
15
Resolution 2 /fX (1.6 s)
3
2 /fX (25.6 s)
7
27/fX (25.6 s) 1/fXT (30.5 s)
1/fXT (30.5 s)
Remarks 1. fX:
Main system clock oscillation frequency
2. fXT: Subsystem clock oscillation frequency 3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.
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(2)
External event counter The number of pulses of an externally input signal can be measured.
(3)
Square-wave output A square wave of any frequency can be output. Table 7-4. Square-Wave Output Range of 8-Bit Timer 02
Minimum Pulse Width Maximum Pulse Width 2 /fX (409.6 s)
11
Resolution 2 /fX (1.6 s)
3
2 /fX (1.6 s)
3
27/fX (25.6 s) 1/fXT (30.5 s)
215/fX (6.55 ms) 28/fXT (7.81 ms)
27/fX (25.6 s) 1/fXT (30.5 s)
Remarks 1. fX:
Main system clock oscillation frequency
2. fXT: Subsystem clock oscillation frequency 3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.
7.2 Configuration of 8-Bit Timer/Event Counters 00 to 02
8-bit timer/event counters 00 to 02 consist of the following hardware. Table 7-5. Configuration of 8-Bit Timer/Event Counters 00 to 02
Item Timer counter Register Timer output Control registers 8 bits x 3 (TM00, TM01, and TM02) Compare register: 8 bits x 3 (CR00, CR01, and CR02) 1 (TO2) 8-bit timer mode control registers 00, 01, and 02 (TMC00, TMC01, and TMC02) Port mode register 2 (PM2) Configuration
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Figure 7-1. Block Diagram of 8-Bit Timer/Event Counter 00
Internal bus
8-bit compare register 00 (CR00) Match INTTM00 fX/2
6
Selector
fX/29 TI0/P24/INTP0
8-bit timer counter 00 (TM00) Clear Selector
2
TCE00 TCL001 TCL000 8-bit timer mode control register 00 (TMC00) Internal bus
Figure 7-2. Block Diagram of 8-Bit Timer/Event Counter 01
Internal bus
8-bit compare register 01 (CR01) Match INTTM01 fX/24 fX/28 TI1/P25/INTP1 2
Selector
8-bit timer counter 01 (TM01) Clear Selector
TCE01 TCL011 TCL010 8-bit timer mode control register 01 (TMC01) Internal bus
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Figure 7-3. Block Diagram of 8-Bit Timer 02
Internal bus
8-bit compare register 02 (CR02) Match
P23 output latch
PM23
INTTM02 fX/23
Selector
fX/27 fXT
8-bit timer counter 02 (TM02) Clear Selector
Selector
F/F ComparatorNote
TO2/CMPTOUT0/ P23
2
TCE02 TCL021 TCL020 TOE02 8-bit timer mode control register 02 (TMC02) Internal bus bus Internal
Note See CHAPTER 12 COMPARATOR for details of the comparator. (1) 8-bit compare register 0n (CR0n) This is an 8-bit register that compares the value set to CR0n with the 8-bit timer counter 0n (TM0n) count value, and if they match, an interrupt request (INTTM0n) is generated. CR0n is set using an 8-bit memory manipulation instruction. Values from 00H to FFH can be set. RESET input makes CR0n undefined. Caution Be sure to stop the operation of the timer before rewriting CR0n. If CR0n is rewritten while the timer is operation-enabled, an interrupt request match signal may be generated at the time of the rewrite. Remark (2) n = 0 to 2
8-bit timer counter 0n (TM0n) This is an 8-bit register that counts pulses. TM0n is read using an 8-bit memory manipulation instruction. RESET input sets TM0n to 00H. Remark n = 0 to 2
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7.3 Registers Controlling 8-Bit Timer/Event Counters 00 to 02
The following two registers are used to control 8-bit timer/event counters 00 to 02. * 8-bit timer mode control registers 00, 01, and 02 (TMC00, TMC01, and TMC02) * Port mode register 2 (PM2) (1) 8-bit timer mode control register 00 (TMC00) TMC00 enables/stops operation of 8-bit timer counter 00 (TM00) and sets the count clock of TM00. TMC00 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMC00 to 00H. Figure 7-4. Format of 8-Bit Timer Mode Control Register 00
Symbol TMC00 <7> TCE00 6 0 5 0 4 0 3 0 2 1 0 0 Address FF53H After reset 00H R/W R/W
TCL001 TCL000
TCE00 0 1
Operation control of 8-bit timer counter 00 Operation stopped (TM00 is cleared to 00H) Operation enabled
TCL001 TCL000 0 0 1 1 0 1 0 1 fX/26 (78.1 kHz) fX/29 (9.76 kHz)
Count clock selection of 8-bit timer/event counter 00
Rising edge of TI0 Falling edge of TI0
Caution
Be sure to stop the operation of the timer before setting TMC00.
Remarks 1. fX: Main system clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz.
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(2)
8-bit timer mode control register 01 (TMC01) TMC01 determines whether to enable or stop operation of 8-bit timer counter 01 (TM01) and specifies the count clock for 8-bit timer/event counter 01. TMC01 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMC01 to 00H. Figure 7-5. Format of 8-Bit Timer Mode Control Register 01
Symbol TMC01
<7> TCE01
6 0
5 0
4 0
3 0
2
1
0 0
Address FF57H
After reset 00H
R/W R/W
TCL011 TCL010
TCE01 0 1
Operation control of 8-bit timer counter 01 Operation stopped (TM01 is cleared to 00H) Operation enabled
TCL011 TCL010 0 0 1 1 0 1 0 1 fX/24 (312.5 kHz) fX/28 (19.5 kHz) Rising edge of TI1 Falling edge of TI1
Count clock selection of 8-bit timer/event counter 01
Caution
Be sure to stop the operation of the timer before setting TMC01.
Remarks 1. fX: Main system clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz.
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(3)
8-bit timer mode control register 02 (TMC02) TMC02 determines whether to enable or stop operation of 8-bit timer counter 02 (TM02) and specifies the count clock for 8-bit timer 02. It also controls the operation of the output controller. TMC02 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMC02 to 00H. Figure 7-6. Format of 8-Bit Timer Mode Control Register 02
Symbol TMC02
<7> TCE02
6 0
5 0
4 0
3 0
2
1
<0>
Address FF5BH
After reset 00H
R/W R/W
TCL021 TCL020 TOE02
TCE02 0 1
Operation control of 8-bit timer counter 02 Operation stopped (TM02 is cleared to 00H) Operation enabled
TCL021 TCL020 0 0 1 1 0 1 0 1 fX/23 (625 kHz) fX/27 (39.1 kHz) fXT (32.768 kHz) Setting prohibited
Count clock selection of 8-bit timer 02
TOE02 0 1 Output disabled (port mode) Output enabled
Output control of 8-bit timer 02
Caution
Be sure to stop the operation of the timer before setting TMC02. Main system clock oscillation frequency
Remarks 1. fX:
2. fXT: Subsystem clock oscillation frequency 3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.
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(4)
Port mode register 2 (PM2) This register sets port 2 to input/output in 1-bit units. When using the P23/COMPTOUT0/TO2 pin for timer output, set PM23 and the output latch of P23 to 0. PM2 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM2 to FFH. Figure 7-7. Format of Port Mode Register 2
Symbol PM2
7
6
5
4
3
2
1
0
Address FF22H
After reset FFH
R/W R/W
PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20
PM23 0 1 Output mode (output buffer on) Input mode (output buffer off)
P23 pin I/O mode selection
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7.4 Operation of 8-Bit Timer/Event Counters 00 to 02
7.4.1 Operation as interval timer The interval timer repeatedly generates an interrupt at time intervals specified by the count value set to 8-bit compare registers 00, 01, and 02 (CR00, CR01, and CR02) in advance. To operate the 8-bit timer/event counter as an interval timer, make the settings in the following order. <1> Set 8-bit timer counter 0n (TM0n) to operation-disabled (TCE0n (bit 7 of 8-bit timer mode control register 0n (TMC0n)) = 0) <2> Select the count clock of the 8-bit timer/event counter (see Tables 7-6 to 7-8) <3> Set the count value to CR0n <4> Set TM0n to operation-enabled (TCE0n = 1) When the count value of 8-bit timer counter 0n (TM0n) matches the value set to CR0n, the value of TM0n is cleared to 00H and TM0n continues counting. At the same time, an interrupt request signal (INTTM0n) is generated. Tables 7-6 through 7-8 show the interval time, and Figures 7-8 and 7-9 show the timing of interval timer operation. Caution When the setting of the count clock using TMC0n and the setting of the TM0n to operationenable using an 8-bit memory manipulation instruction are performed at the same time, an error of one clock or more may occur in the first cycle after the timer is started. Because of this, when the 8-bit timer/event counter operates as an interval timer, be sure to make the settings in the order described above. Remark n = 0 to 2 Table 7-6. Interval Time of 8-Bit Timer/Event Counter 00
TCL001 0 0 1 1 TCL000 0 1 0 1 Minimum Interval Time 26/fX (12.8 s) 29/fX (102.4 s) TI0 input cycle TI0 input cycle Maximum Interval Time 214/fX (3.28 ms) 217/fX (26.2 ms) 28 x TI0 input cycle 2 x TI0 input cycle
8
Resolution 26/fX (12.8 s) 29/fX (102.4 s) TI0 input edge cycle TI0 input edge cycle
Remarks 1. fX: Main system clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz. Table 7-7. Interval Time of 8-Bit Timer/Event Counter 01
TCL011 0 0 1 1 TCL010 0 1 0 1
4
Minimum Interval Time 2 /fX (3.2 s) 28/fX (51.2 s) TI1 input cycle TI1 input cycle
12
Maximum Interval Time 2 /fX (819.2 s) 216/fX (13.1 ms) 28 x TI1 input cycle 2 x TI1 input cycle
8 4
Resolution 2 /fX (3.2 s) 28/fX (51.2 s) TI1 input edge cycle TI1 input edge cycle
Remarks 1. fX: Main system clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz.
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Table 7-8. Interval Time of 8-Bit Timer 02
TCL021 0 0 1 1 TCL020 0 1 0 1
3
Minimum Interval Time 2 /fX (1.6 s) 27/fX (25.6 s) 1/fXT (30.5 s) Setting prohibited
11
Maximum Interval Time 2 /fX (409.6 s) 215/fX (6.55 ms) 28/fXT (7.81 ms)
3
Resolution 2 /fX (1.6 s) 27/fX (25.6 s) 1/fXT (30.5 s)
Remarks 1. fX:
Main system clock oscillation frequency
2. fXT: Subsystem clock oscillation frequency 3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz. Figure 7-8. Interval Timer Operation Timing of Timer 00 and Timer 01
t
Count clock
TM0n count value
00
01
N
00 Clear
01
N
00 Clear
01
N
CR0n
N
N
N
N
TCE0n Count start INTTM0n Interrupt acknowledged Interval time Interval time Interrupt acknowledged Interval time
Remarks 1. Interval time = (N + 1) x t where N = 00H to FFH 2. n = 0, 1
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Figure 7-9. Interval Timer Operation Timing of Timer 02
t
Count clock
TM02 count value
00
01
N
00 Clear
01
N
00 Clear
01
N
CR02
N
N
N
N
TCE02 Count start INTTM02 Interrupt acknowledged TO2 Interrupt acknowledged
Interval time
Interval time
Interval time
Remark
Interval time = (N + 1) x t where N = 00H to FFH
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 00 TO 02
7.4.2 Operation as external event counter (timer 00 and timer 01 only) The external event counter counts the number of external clock pulses input to the TI0/P24/INTP0 and TI1/P25/INTP1 pins by using 8-bit timer counters 00 and 01 (TM00 and TM01). To operate 8-bit timer/event counters 00 and 01 as an external event counter, make the settings in the following order. <1> Set P24 and P25 to input mode (PM24 = 1, PM25 = 1) <2> Set 8-bit timer counter 0n (TM0n) to operation-disabled (TCE0n (bit 7 of 8-bit timer mode control register 0n (TMC0n)) = 0) <3> Specify the rising edge/falling edge of TIn (see Tables 7-6 and 7-7) <4> Set the count value to CR0n <5> Set TM0n to operation-enabled (TCE0n = 1) Each time the valid edge specified by bit 1 (TCL0n0) of TMC0n is input, the value of 8-bit timer counter 0n (TM0n) is incremented. When the count value of TM0n matches the value set to CR0n, the value of TM0n is cleared to 00H and TM0n continues counting. At the same time, an interrupt request signal (INTTM0n) is generated. Figure 7-10 shows the timing of external event counter operation (with rising edge specified). Caution When the setting of the count clock using TMC0n and the setting of the TM0n to operationenable using an 8-bit memory manipulation instruction are performed at the same time, an error of one clock or more may occur in the first cycle after the timer is started. Because of this, when the 8-bit timer/event counter operates as an external event counter, be sure to make the settings in the order described above. Remark n = 0, 1 Figure 7-10. External Event Counter Operation Timing (with Rising Edge Specified)
TIn pin input
TM0n count value
00
01
02
03
04
05
N-1
N
00
01
02
03
CR0n
N
TCE0n
INTTM0n
Remarks 1. N = 00H to FFH 2. n = 0, 1
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 00 TO 02
7.4.3 Operation as square-wave output (timer 02 only) The 8-bit timer can generate a square-wave output of any frequency at intervals specified by the count value preset to 8-bit compare register 02 (CR02). To operate 8-bit timer 02 as a square-wave output, make the settings in the following order. <1> Set P23 to output mode (PM23 = 0), and set the output latch of P23 to 0 <2> Disable 8-bit timer counter 02 (TM02) operation (TCE02 (bit 0 of 8-bit timer mode control register 02 (TMC02)) = 1) <3> Set the count clock of 8-bit timer 02 (see Table 7-9), and enable TO2 to output (TOE02 (bit 0 of TMC02) = 1) <4> Set the count value to CR02 <5> Enable TM02 operation (TCE02 = 1) When the count value of 8-bit timer counter 02 (TM02) matches the value set in CR02, the TO2/P23/CMPTOUT0 pin output is inverted. Through application of this mechanism, square waves of any frequency can be output. As soon as a match occurs, the TM02 value is cleared to 00H, then counting continues count and an interrupt request signal (INTTM02) is generated. Setting bit 7 of TMC02 (TCE02) to 0 clears the square-wave output to 0. Table 7-9 lists the square-wave output range, and Figure 7-11 shows the timing of square-wave output. Caution When the setting of the count clock using TMC02 and the setting of the TM02 to operationenable using an 8-bit memory manipulation instruction are performed at the same time, an error of one clock or more may occur in the first cycle after the timer is started. Because of this, when the 8-bit timer operates as a square-wave output, be sure to make the settings in the order described above. Table 7-9. Square-Wave Output Range of 8-Bit Timer 02
TCL021 0 0 1 1 TCL020 0 1 0 1 Minimum Pulse Width 23/fX (1.6 s) 27/fX (25.6 s) 1/fXT (30.5 s) Setting prohibited Maximum Pulse Width 211/fX (409.6 s) 215/fX (6.55 ms) 28/fXT (7.81 ms) Resolution 23/fX (1.6 s) 27/fX (25.6 s) 1/fXT (30.5 s)
Remarks 1. fX:
Main system clock oscillation frequency
2. fXT: Subsystem clock oscillation frequency 3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.
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Figure 7-11. Square-Wave Output Timing
Count clock
TM02 count value
00
01
N
00 Clear
01
N
00 Clear
01
N
CR02
N
N
N
N
TCE02 Count start INTTM02 Interrupt acknowledged TO2Note Interrupt acknowledged
Note The initial value of TO2 when output is enabled (TOE02 = 1) becomes low level.
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 00 TO 02
7.5 Cautions on Using 8-Bit Timer/Event Counters 00 to 02
(1) Error on starting timer An error of up to 1 clock occurs after the timer has been started until a match signal is generated. This is because 8-bit timer counters 00, 01, and 02 (TM00, TM01, and TM02) are started asynchronous to the count pulse. Figure 7-12. Start Timing of 8-Bit Timer Counters 00, 01, and 02
Count pulse
TM00, TM01, TM02 count value
00H
01H
02H
03H
04H
Timer starts
(2)
Setting of 8-bit compare register 8-bit compare registers 00, 01, and 02 (CR00, CR01, and CR02) can be set to 00H. Therefore, one pulse can be counted when an 8-bit timer/event counter operates as an event counter. Figure 7-13. External Event Counter Operation Timing
TI0, TI1 input
CR00, CR01
00H
TM00, TM01 count value Interrupt request flag
00H
00H
00H
00H
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CHAPTER 8 WATCH TIMER
8.1 Functions of Watch Timer
The watch timer has the following functions. * Watch timer * Interval timer The watch and interval timers can be used at the same time. Figure 8-1 is a block diagram of the watch timer. Figure 8-1. Block Diagram of Watch Timer
Clear Selector fX/2
7
fW fW 24
9-bit prescaler fW 25 fW 26 fW 27 fW 28 fW 29 Selector
5-bit counter Clear
INTWT
fXT
INTWTI
WTM7 WTM6 WTM5 WTM4 WTM1 WTM0 Watch timer mode control register (WTM) Internal bus
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(1)
Watch timer The 4.19 MHz main system clock or 32.768 kHz subsystem clock is used to issue an interrupt request (INTWT) at 0.5-second intervals. Caution When the main system clock is operating at 5.0 MHz, it cannot be used to generate a 0.5-second interval. In this case, the subsystem clock, which operates at 32.768 kHz, should be used instead.
(2)
Interval timer The interval timer is used to generate an interrupt request (INTWT) at specified intervals. Table 8-1. Interval Time of Interval Timer
Interval Operation at fX = 5.0 MHz 409.6 s 819.2 s 1.64 ms 3.28 ms 6.55 ms 13.1 ms Operation at fX = 4.19 MHz 489 s 978 s 1.96 ms 3.91 ms 7.82 ms 15.6 ms Operation at fXT = 32.768 kHz 488 s 977 s 1.95 ms 3.91 ms 7.81 ms 15.6 ms
2 x 1/fW
4
2 x 1/fW
5
2 x 1/fW
6
2 x 1/fW
7
28 x 1/fW 2 x 1/fW
9
Remark
fW: Watch timer clock frequency (fX/2 or fXT) fX: Main system clock oscillation frequency fXT: Subsystem clock oscillation frequency
7
8.2 Configuration of Watch Timer
The watch timer consists of the following hardware. Table 8-2. Configuration of Watch Timer
Item Counter Prescaler Control register 5 bits x 1 9 bits x 1 Watch timer mode control register (WTM) Configuration
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8.3 Register Controlling Watch Timer
The watch timer mode control register (WTM) is used to control the watch timer. * Watch timer mode control register (WTM) WTM selects a count clock for the watch timer and specifies whether to enable operation of the timer. It also specifies the prescaler interval and how the 5-bit counter is controlled. WTM is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets WTM to 00H. Figure 8-2. Format of Watch Timer Mode Control Register
Symbol 7 6 5 4 3 0 2 0 1 0 Address FF4AH After reset 00H R/W R/W
WTM WTM7 WTM6 WTM5 WTM4
WTM1 WTM0
WTM7 0 1 fX/27 (39.1 kHz) fXT (32.768 kHz)
Watch timer count clock selection
WTM6 WTM5 WTM4 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 24/fW (488 s) 25/fW (977 s) 26/fW (1.95 ms) 27/fW (3.91 ms) 28/fW (7.81 ms) 29/fW (15.6 ms) Setting prohibited
Prescaler interval selection
Other than above
WTM1 0 1 Cleared after stop Started
Control of 5-bit counter operation
WTM0 0 1
Watch timer operation Operation stopped (both prescaler and timer cleared) Operation enabled
Remarks 1. fW: 2. fX:
Watch timer clock frequency (fX/2 or fXT) Main system clock oscillation frequency
7
3. fXT: Subsystem clock oscillation frequency 4. The parenthesized values apply to operation at fW = 32.768 kHz.
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8.4 Operation of Watch Timer
8.4.1 Operation as watch timer The main system clock (4.19 MHz) or subsystem clock (32.768 kHz) is used as a watch timer that generates interrupts at 0.5-second intervals. By setting bits 0 and 1 (WTM0 and WTM1) of the watch timer mode control register (WTM) to 1, the watch timer starts counting. By setting them to 0, the 5-bit counter is cleared and the watch timer stops counting. When the interval timer also operates at the same time by setting WTM1 to 0, only the watch timer can be started from 0 seconds. However, an error of up to 2 x 1/fW seconds may occur for the first overflow of the watch timer
9
(INTWT) after a 0-second start, because the 9-bit prescaler is not cleared in this case. 8.4.2 Operation as interval timer The interval timer is used to repeatedly generate an interrupt request at the interval specified by a preset count value. The interval time can be selected by bits 4 to 6 (WTM4 to WTM6) of the watch timer mode control register (WTM). Table 8-3. Interval Time of Interval Timer
WTM6 WTM5 WTM4 Interval Operation at fX = 5.0 MHz 409.6 s 819.2 s 1.64 ms 3.28 ms 6.55 ms 13.1 ms Operation at fX = 4.19 MHz 489 s 978 s 1.96 ms 3.91 ms 7.82 ms 15.6 ms Operation at fXT = 32.768 kHz 488 s 977 s 1.95 ms 3.91 ms 7.81 ms 15.6 ms
0 0 0 0 1 1
0 0 1 1 0 0
0 1 0 1 0 1
24 x 1/fW 25 x 1/fW 2 x 1/fW
6
2 x 1/fW
7
2 x 1/fW
8
2 x 1/fW
9
Other than above
Setting prohibited
Remark
fX: Main system clock oscillation frequency fXT: Subsystem clock oscillation frequency fW: Watch timer clock frequency
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Figure 8-3. Watch Timer/Interval Timer Operation Timing
5-bit counter 0H Start Count clock fW/29 Watch timer interrupt INTWT Interval timer interrupt INTWTI Interval timer (T) T Overflow Overflow
Watch timer interrupt time (0.5 s)
Watch timer interrupt time (0.5 s)
Remark
fW: Watch timer clock frequency The parenthesized values apply to operation at fW = 32.768 kHz.
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CHAPTER 9 WATCHDOG TIMER
9.1 Functions of Watchdog Timer
The watchdog timer has the following functions. * Watchdog timer * Interval timer Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode register (WDTM). (1) Watchdog timer The watchdog timer is used to detect an inadvertent program loop. When the program loop is detected, a non-maskable interrupt or the RESET signal can be generated. Table 9-1. Program Loop Detection Time of Watchdog Timer
Program Loop Detection Time 2 x 1/fX
11
Operation at fX = 5.0 MHz 410 s 1.64 ms 6.55 ms 26.2 ms
213 x 1/fX 2 x 1/fX
15
2 x 1/fX
17
fX: Main system clock oscillation frequency (2) Interval timer The interval timer generates an interrupt at any intervals set in advance. Table 9-2. Interval Time
Interval Time 211 x 1/fX 2 x 1/fX
13
Operation at fX = 5.0 MHz 410 s 1.64 ms 6.55 ms 26.2 ms
2 x 1/fX
15
2 x 1/fX
17
fX: Main system clock oscillation frequency
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CHAPTER 9 WATCHDOG TIMER
9.2 Configuration of Watchdog Timer
The watchdog timer consists of the following hardware. Table 9-3. Configuration of Watchdog Timer
Item Control registers Timer clock selection register 2 (TCL2) Watchdog timer mode register (WDTM) Configuration
Figure 9-1. Block Diagram of Watchdog Timer
Internal bus
fX 24 fX 26
Prescaler fX 28 fX 210
TMMK4
TMIF4
Selector
INTWDT maskable interrupt request RESET INTWDT non-maskable interrupt request
7-bit counter Clear
Controller
3
TCL22 TCL21 TCL20 Timer clock selection register 2 (TCL2)
RUN WDTM4 WDTM3 Watchdog timer mode register (WDTM) Internal bus
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CHAPTER 9 WATCHDOG TIMER
9.3 Registers Controlling Watchdog Timer
The following two registers are used to control the watchdog timer. * Timer clock selection register 2 (TCL2) * Watchdog timer mode register (WDTM) (1) Timer clock selection register 2 (TCL2) This register sets the watchdog timer count clock. TCL2 is set using an 8-bit memory manipulation instruction. RESET input sets TCL2 to 00H. Figure 9-2. Format of Timer Clock Selection Register 2
Symbol TCL2 7 0 6 0 5 0 4 0 3 0 2 1 0 Address FF42H After reset 00H R/W R/W
TCL22 TCL21 TCL20
TCL22 TCL21 TCL20 0 0 1 1 0 1 0 1 0 0 0 0
Watchdog timer count clock selection fX/24 (312.5 kHz) fX/26 (78.1 kHz) fX/28 (19.5 kHz) fX/210 (4.88 kHz) Setting prohibited 211/fX (410 s) 213/fX (1.64 ms) 215/fX (6.55 ms) 217/fX (26.2 ms)
Interval time
Other than above
Remarks 1. fX: Main system clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz.
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(2)
Watchdog timer mode register (WDTM) This register sets the operation mode of the watchdog timer, and enables/disables counting of the watchdog timer. WDTM is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets WDTM to 00H. Figure 9-3. Format of Watchdog Timer Mode Register
Symbol WDTM
<7> RUN
6 0
5 0
4
3
2 0
1 0
0 0
Address FFF9H
After reset 00H
R/W R/W
WDTM4 WDTM3
RUN 0 1 Stop counting
Selection of operation of watchdog timerNote 1
Clear counter and start counting
WDTM4 WDTM3 0 0 1 1 0 1 0 1 Operation stopped
Selection of operation mode of watchdog timerNote 2
Interval timer mode (overflow and maskable interrupt occur)Note 3 Watchdog timer mode 1 (overflow and non-maskable interrupt occur) Watchdog timer mode 2 (overflow occurs and reset operation started)
Notes 1. Once RUN has been set to (1), it cannot be cleared to (0) by software. Therefore, when counting is started, it cannot be stopped by any means other than RESET input. 2. Once WDTM3 and WDTM4 have been set to (1), they cannot be cleared to (0) by software. 3. The watchdog timer starts operation as an interval timer when RUN is set to 1. Cautions 1. When the watchdog timer is cleared by setting RUN to 1, the actual overflow time is up to 0.8% shorter than the time set by timer clock selection register 2 (TCL2). 2. In watchdog timer mode 1 or 2, set WDTM4 to 1 after confirming that TMIF4 (bit 0 of interrupt request flag register 0 (IF0)) is set to 0. While TMIF4 is 1, a non-maskable interrupt is generated upon write completion if watchdog timer mode 1 or 2 is selected.
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CHAPTER 9 WATCHDOG TIMER
9.4 Operation of Watchdog Timer
9.4.1 Operation as watchdog timer The watchdog timer detects an inadvertent program loop when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1. The count clock (program loop detection time interval) of the watchdog timer can be selected by bits 0 to 2 (TCL20 to TCL22) of timer clock selection register 2 (TCL2). By setting bit 7 (RUN) of WDTM to 1, the watchdog timer is started. Set RUN to 1 within the set program loop detection time interval after the watchdog timer has been started. By setting RUN to 1, the watchdog timer can be cleared and start counting. If RUN is not set to 1, and the program loop detection time is exceeded, the system is reset or a non-maskable interrupt is generated by the value of bit 3 (WDTM3) of WDTM. The watchdog timer continues operation in the HALT mode, but stops in the STOP mode. Therefore, set RUN to 1 before entering the STOP mode to clear the watchdog timer, and then execute the STOP instruction. Cautions 1. The actual program loop detection time may be up to 0.8% shorter than the set time. 2. When the subsystem clock is selected as the CPU clock, the watchdog timer stops counting. Table 9-4. Program Loop Detection Time of Watchdog Timer
TCL22 0 0 1 1 TCL21 0 1 0 1 TCL20 0 0 0 0
11
Program Loop Detection Time 2 x 1/fX 2 x 1/fX
13
Operation at fX = 5.0 MHz 410 s 1.64 ms 6.55 ms 26.2 ms
2 x 1/fX
15
217 x 1/fX
fX: Main system clock oscillation frequency
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9.4.2 Operation as interval timer When bit 4 (WDTM4) and bit 3 (WDTM3) of the watchdog timer mode register (WDTM) are set to 0 and 1, respectively, the watchdog timer also operates as an interval timer that repeatedly generates an interrupt at time intervals specified by a preset count value. Select the count clock (or interval time) by setting bits 0 to 2 (TCL20 to TCL22) of timer clock selection register 2 (TCL2). The watchdog timer starts operation as an interval timer when the RUN bit (bit 7 of WDTM) is set to 1. In the interval timer mode, the interrupt mask flag (TMMK4) is valid, and a maskable interrupt (INTWDT) can be generated. The priority of INTWDT is set as the highest of all the maskable interrupts. The interval timer continues operation in the HALT mode, but stops in the STOP mode. Therefore, set RUN to 1 before entering the STOP mode to clear the interval timer, and then execute the STOP instruction. Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (when the watchdog timer mode is selected), the interval timer mode is not set, unless the RESET signal is input. 2. The interval time immediately after the setting by WDTM may be up to 0.8% shorter than the set time. Table 9-5. Interval Time of Interval Timer
TCL22 0 0 1 1 TCL21 0 1 0 1 TCL20 0 0 0 0 2 x 1/fX
11
Interval Time
Operation at fX = 5.0 MHz 410 s 1.64 ms 6.55 ms 26.2 ms
213 x 1/fX 2 x 1/fX
15
2 x 1/fX
17
fX: Main system clock oscillation frequency
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CHAPTER 10 8-BIT A/D CONVERTER (PD789407A SUBSERIES)
10.1 Function of 8-Bit A/D Converter
The 8-bit A/D converter converts input analog voltages to digital signals with an 8-bit resolution. It can control up to seven analog input channels (ANI0 to ANI6). A/D conversion can be started only by software. One of analog inputs ANI0 to ANI6 is selected for A/D conversion. A/D conversion is performed repeatedly, with an interrupt request (INTAD0) being issued each time an A/D conversion is completed.
10.2 Configuration of 8-Bit A/D Converter
The 8-bit A/D converter consists of the following hardware. Table 10-1. Configuration of 8-Bit A/D Converter
Item Analog inputs Registers 7 channels (ANI0 to ANI6) Successive approximation register (SAR) A/D conversion result register 0 (ADCR0) A/D converter mode register 0 (ADM0) A/D input selection register 0 (ADS0) Configuration
Control registers
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CHAPTER 10 8-BIT A/D CONVERTER (PD789407A SUBSERIES)
Figure 10-1. Block Diagram of 8-Bit A/D Converter
Series resistor string AVDD AVREF P-ch ANI0/P60 ANI1/P61 ANI2/P62 ANI3/P63 ANI4/P64 ANI5/P65 ANI6/P66 Sample & hold circuit
Selector Tap selector
Voltage comparator
AVSS
AVSS
Successive approximation register (SAR)
Controller
INTAD0
3 ADS02 ADS01 ADS00 ADCS0 FR02 FR01 FR00 A/D converter mode register 0 (ADM0) Internal bus
A/D conversion result register 0 (ADCR0)
A/D input selection register 0 (ADS0)
(1)
Successive approximation register (SAR) The SAR receives the result of comparing an analog input voltage and a voltage at a voltage tap (comparison voltage), received from the series resistor string, starting from the most significant bit (MSB). Upon receiving all the bits, down to the least significant bit (LSB), that is, upon the completion of A/D conversion, the SAR sends its contents to A/D conversion result register 0 (ADCR0).
(2)
A/D conversion result register 0 (ADCR0) ADCR0 holds the result of A/D conversion. Each time A/D conversion ends, the conversion result received from the successive approximation register is loaded into ADCR0, which is an 8-bit register that holds the result of A/D conversion. ADCR0 is read using an 8-bit memory manipulation instruction. RESET input makes ADCR0 undefined.
(3)
Sample & hold circuit The sample & hold circuit samples consecutive analog inputs from the input circuit, one by one, and sends them to the voltage comparator. The sampled analog input voltage is held during A/D conversion.
(4)
Voltage comparator The voltage comparator compares an analog input with the voltage output by the series resistor string.
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(5)
Series resistor string The series resistor string is configured between AVREF and AVSS. against which analog inputs are compared. It generates the reference voltages
(6)
ANI0 to ANI6 pins The ANI0 to ANI6 pins are analog input pins for the seven-channel A/D converter. They are used to receive the analog signals to be subject to A/D conversion. Caution Do not supply the ANI0 to ANI6 pins with voltages that fall outside the rated range. If a voltage greater than AVREF or less than AVSS (even if within the absolute maximum rating) is supplied to any of these pins, the conversion value for the corresponding channel will be undefined. Furthermore, the conversion values for the other channels may also be affected.
(7)
AVREF pin The AVREF pin is a reference voltage pin for the A/D converter. Signals received at the ANI0 to ANI6 pins are converted to digital signals based on the voltage across the AVREF and AVSS pins.
(8)
AVSS pin The AVSS pin is a ground potential pin for the A/D converter. This pin must be held at the same potential as the VSS0 pin, even while the A/D converter is not being used.
(9)
AVDD pin The AVDD pin is an analog power supply pin for the A/D converter. This pin must be held at the same potential as the VDD0 pin, even while the A/D converter is not being used.
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CHAPTER 10 8-BIT A/D CONVERTER (PD789407A SUBSERIES)
10.3 Registers Controlling 8-Bit A/D Converter
The following two registers are used to control the 8-bit A/D converter. * A/D converter mode register 0 (ADM0) * A/D input selection register 0 (ADS0) (1) A/D converter mode register 0 (ADM0) ADM0 specifies the conversion time for analog inputs. It also specifies whether to enable conversion. ADM0 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADM0 to 00H. Figure 10-2. Format of A/D Converter Mode Register 0
Symbol <7> ADM0 ADCS0 6 0 5 4 3 2 0 1 0 0 0 Address FF80H After reset 00H R/W R/W
FR02 FR01 FR00
ADCS0 0 1 Conversion stopped Conversion enabled
A/D conversion control
FR02 FR01 FR00 0 0 0 1 1 1 0 0 1 0 0 1 0 1 0 0 1 0 144/fx 120/fx 96/fx 72/fx 60/fx 48/fx (28.8 s) (24 s) (19.2 s) (14.4 s)
A/D conversion time selectionNote 1
(Setting prohibitedNote 2) (Setting prohibitedNote 2)
Other than above
Setting prohibited
Notes 1. The specifications of FR02, FR01, and FR00 must be such that the A/D conversion time is at least 14 s. 2. These bit combinations must not be used, as the A/D conversion time will fall below 14 s. Cautions 1. The result of conversion performed immediately after bit 7 (ADCS0) is set is undefined. 2. The result of conversion performed after ADCS0 is cleared may be undefined (see 10.5 (5) Timing that makes the A/D conversion result undefined for details). Remarks 1. fX: Main system clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz.
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(2)
A/D input selection register 0 (ADS0) ADS0 register specifies the port used to input the analog voltages to be converted to a digital signal. ADS0 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADS0 to 00H. Figure 10-3. Format of A/D Input Selection Register 0
Symbol ADS0
7 0
6 0
5 0
4 0
3 0
2
1
0
Address FF84H
After reset 00H
R/W R/W
ADS02 ADS01 ADS00
ADS02 ADS01 ADS00 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 Setting prohibited
Analog input channel specification
Caution
Bits 3 to 7 must be fixed to 0.
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CHAPTER 10 8-BIT A/D CONVERTER (PD789407A SUBSERIES)
10.4 Operation of 8-Bit A/D Converter
10.4.1 Basic operation of 8-bit A/D converter <1> Select a channel for A/D conversion, using A/D input selection register 0 (ADS0). <2> The voltage supplied to the selected analog input channel is sampled using the sample & hold circuit. <3> After sampling continues for a certain period of time, the sample & hold circuit is put on hold to keep the input analog voltage until A/D conversion is completed. <4> Bit 7 of the successive approximation register (SAR) is set. The series resistor string voltage tap at the tap selector is set to half of AVREF. <5> The series resistor string tap voltage is compared with the analog input voltage using the voltage comparator. If the analog input voltage is higher than half of AVREF, the MSB of the SAR remains set. If it is lower than half of AVREF, the MSB is reset. <6> Bit 6 of the SAR is set automatically, and comparison shifts to the next stage. The next voltage tap of the series resistor string is selected according to bit 7, which reflects the previous comparison result, as follows: * Bit 7 = 1: Three quarters of AVREF * Bit 7 = 0: One quarter of AVREF The tap voltage is compared with the analog input voltage. Bit 6 is set or reset according to the result of comparison. * Analog input voltage tap voltage: Bit 6 = 1 * Analog input voltage < tap voltage: Bit 6 = 0 <7> Comparison is repeated until bit 0 of the SAR is reached. <8> When comparison is completed for all of the 8 bits, a significant digital result is left in the SAR. This value is sent to and latched in A/D conversion result register 0 (ADCR0). At the same time, it is possible to generate an A/D conversion end interrupt request (INTAD0). Cautions 1. The first A/D conversion value immediately following the start of A/D conversion may be undefined. 2. When the A/D converter enters the standby mode, it stops operating.
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Figure 10-4. Basic Operation of 8-Bit A/D Converter
Conversion time
Sampling time A/D converter operation
Sampling
A/D conversion
SAR
Undefined
80H
C0H or 40H
Conversion result
ADCR0
Conversion result
INTAD0
A/D conversion continues until bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) is reset (0) by software. If an attempt is made to write to ADM0 or A/D input selection register 0 (ADS0) during A/D conversion, the current A/D conversion is canceled. In this case, A/D conversion is restarted from the beginning, if the ADCS0 bit is set (1). RESET makes A/D conversion result register 0 (ADCR0) undefined. 10.4.2 Input voltage and conversion result The relationship between the analog input voltage at the analog input pins (ANI0 to ANI6) and the A/D conversion result (A/D conversion result register 0 (ADCR0)) is represented by: ADCR0 = INT ( or (ADCR0 - 0.5) x AVREF 256 VIN < (ADCR0 + 0.5) x AVREF 256 VIN AVREF x 256 + 0.5)
INT( ): Function that returns the integer part of a parenthesized value VIN: AVREF: Analog input voltage AVREF pin voltage
ADCR0: Value in A/D conversion result register 0 (ADCR0) Figure 10-5 shows the relationship between the analog input voltage and the A/D conversion result.
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Figure 10-5. Relationship Between Analog Input Voltage and A/D Conversion Result
255
254
253 A/D conversion result (ADCR0) 3
2
1
0 1 1 3 2 5 3 512 256 512 256 512 256 507 254 509 255 511 512 256 512 256 512 1
Input voltage/AVREF
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10.4.3 Operation mode of 8-bit A/D converter The 8-bit A/D converter is initially in the select mode. In this mode, A/D input selection register 0 (ADS0) is used to select an analog input channel from ANI0 to ANI6 for A/D conversion. A/D conversion can be started only by software, that is, by setting A/D converter mode register 0 (ADM0). The A/D conversion result is saved to A/D conversion result register 0 (ADCR0). At the same time, an interrupt request signal (INTAD0) is generated. * Software-started A/D conversion Setting bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) triggers A/D conversion for a voltage applied to the analog input pin specified in A/D input selection register 0 (ADS0). Upon completion of A/D conversion, the conversion result is saved to A/D conversion result register 0 (ADCR0). At the same time, an interrupt request signal (INTAD0) is generated. Once A/D conversion is activated, and completed, another session of A/D conversion is started. A/D conversion is repeated until new data is written to ADM0. If data where the ADCS0 bit is 1 is written to ADM0 again during A/D conversion, the current session of A/D conversion is discontinued, and a new session of A/D conversion begins for the new data. If data where the ADCS0 bit is 0 is written to ADM0 again during A/D conversion, A/D conversion is stopped immediately. Figure 10-6. Software-Started A/D Conversion
Rewriting ADM0 ADCS0 = 1 Rewriting ADM0 ADCS0 = 1
ADCS0 = 0
A/D conversion
ANIn
ANIn
ANIn
ANIm
ANIm
Conversion is discontinued; no conversion result is preserved.
Stop
ADCR0
ANIn
ANIn
ANIm
INTAD0
Remarks 1. n = 0, 1, ..., 6 2. m = 0, 1, ..., 6
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10.5 Cautions on Using 8-Bit A/D Converter
(1) Current consumption in the standby mode When the A/D converter enters the standby mode, it stops operating. Stopping conversion (bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) = 0) can reduce the current consumption. Figure 10-7 shows how to reduce the current consumption in the standby mode. Figure 10-7. How to Reduce Current Consumption in Standby Mode
AVREF
P-ch
ADCS0
Series resistor string AVSS
(2)
Input range for the ANI0 to ANI6 pins Be sure to keep the input voltage at ANI0 to ANI6 within the rated range. If a voltage greater than AVREF or less than AVSS (even within the absolute maximum rating) is input to a conversion channel, the conversion output of the channel becomes undefined, and the conversion output of the other channels may also be affected.
(3)
Conflict <1> Conflict between writing to A/D conversion result register 0 (ADCR0) at the end of conversion and reading from the ADCR0 bit Reading from the ADCR0 bit takes precedence. After reading, the new conversion result is written to the ADCR0 bit. <2> Conflict between writing to the ADCR0 bit at the end of conversion and writing to A/D converter mode register 0 (ADM0) or A/D input selection register 0 (ADS0) Writing to ADM0 or ADS0 takes precedence. A request to write to the ADCR0 bit is ignored. No A/D conversion end interrupt request signal (INTAD0) is generated.
(4)
Conversion results immediately following start of A/D conversion The first A/D conversion value immediately following the start of A/D conversion may be undefined. Be sure to poll the A/D conversion end interrupt request (INTAD0) and perform processing such as discarding the first conversion result.
(5)
Timing that makes the A/D conversion result undefined If the timing of the end of A/D conversion and the timing of the stop of operation of the A/D converter conflict, the A/D conversion value may be undefined. Because of this, be sure to read out the A/D conversion result while the A/D converter is in operation. Furthermore, when reading out an A/D conversion result after A/D conversion has stopped, be sure to have done so by the time the next conversion result is complete. The conversion result readout timing is shown in Figures 10-8 and 10-9.
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Figure 10-8. Conversion Result Readout Timing (When Conversion Result Is Undefined Value)
A/D conversion end A/D conversion end
ADCR0 INTAD0 ADCS0
Normal conversion result
Undefined value
Normal conversion result read out
A/D operation stopped
Undefined value read out
Figure 10-9. Conversion Result Readout Timing (When Conversion Result Is Normal Value)
A/D conversion end
ADCR0 INTAD0 ADCS0
Normal conversion result
A/D operation stopped
Normal conversion result read out
(6)
Noise elimination To maintain a resolution of 8 bits, it is necessary to avoid noise at the AVREF and ANI0 to ANI6 pins. The higher the output impedance of the analog input source, the larger the effect by noise. To eliminate noise, attach an external capacitor to the relevant pins as shown in Figure 10-10.
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Figure 10-10. Analog Input Pin Processing
If noise greater than AVREF or less than AVSS is likely to come to the AVREF pin, clamp the voltage at the pin by attaching a diode with a small VF (0.3 V or lower).
Reference voltage input
AVREF
C = 100 to 1000 pF
VDD0 AVDD AVSS VSS0
(7)
ANI0 to ANI6 The analog input pins (ANI0 to ANI6) are alternate-function pins. They are also used as port pins (P60 to P66). If any of ANI0 to ANI6 has been selected for A/D conversion, do not execute input instructions for the ports. Otherwise, the conversion resolution may become lower. If a digital pulse is applied to a pin adjacent to the analog input pins during A/D conversion, coupling noise may occur which prevents an A/D conversion result from being attained as expected. Avoid applying a digital pulse to pins adjacent to the analog input pins during A/D conversion.
(8)
Input impedance of ANI0 to ANI6 pins This A/D converter charges the internal sampling capacitor for about 1/10 of the conversion time, and performs sampling. Therefore at times other than sampling, only the leak current is output. During sampling, the current for charging the capacitor is also output, so the input impedance fluctuates and has no meaning. However, to ensure adequate sampling, it is recommended that the output impedance of the analog input source be set to below 10 k, or a 100 pF capacitor be connected to the ANI0 to ANI6 pins (see Figure 1010).
(9)
Input impedance of the AVREF pin A series resistor string of several tens of k is connected across the AVREF and AVSS pins. If the output impedance of the reference voltage source is high, this high impedance is eventually connected in parallel with the series resistor string across the AVREF and AVSS pins, leading to a higher reference voltage error.
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(10) Interrupt request flag (ADIF0) Changing the contents of A/D converter mode register 0 (ADM0) does not clear the interrupt request flag (ADIF0). If the voltage at the analog input pins is changed during A/D conversion, therefore, the A/D conversion result and the conversion end interrupt request flag may reflect the previous analog input just before writing to ADM0. In this case, the ADIF0 may appear to be set if it is read-accessed just after ADM0 is writeaccessed, even when A/D conversion has not been completed for the new analog input. In addition, ADIF0 must be cleared before A/D conversion is restarted. Figure 10-11. A/D Conversion End Interrupt Request Generation Timing
Rewriting to ADM0 (to begin conversion for ANIn) Rewriting to ADM0 (to begin conversion for ANIm)
ADIF0 has been set, but conversion for ANIm has not been completed.
A/D conversion
ANIn
ANIn
ANIm
ANIm
ADCR0
ANIn
ANIn
ANIm
ANIm
INTAD0
Remarks 1. n = 0, 1, ..., 6 2. m = 0, 1, ..., 6 (11) AVDD pin The AVDD pin is used to supply power to the analog circuit. It is also used to supply power to the ANI0 to ANI6 input circuit. If your application is designed to be switched to backup power, the AVDD pin must be supplied with the same voltage level as for the VDD0 pin, as shown in Figure 10-12. Figure 10-12. AVDD Pin Processing
VDD0 Main power source AVDD Backup capacitor VSS0 AVSS
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CHAPTER 11 10-BIT A/D CONVERTER (PD789417A SUBSERIES)
11.1 Function of 10-Bit A/D Converter
The 10-bit A/D converter converts input analog voltages to digital signals with a 10-bit resolution. It can control up to seven analog input channels (ANI0 to ANI6). A/D conversion can be started only by software. One of analog inputs ANI0 to ANI6 is selected for A/D conversion. A/D conversion is performed repeatedly, with an interrupt request (INTAD0) being issued each time an A/D conversion is completed.
11.2 Configuration of 10-Bit A/D Converter
The A/D converter consists of the following hardware. Table 11-1. Configuration of 10-Bit A/D Converter
Item Analog inputs Registers 7 channels (ANI0 to ANI6) Successive approximation register (SAR) A/D conversion result register 0 (ADCR0) A/D converter mode register 0 (ADM0) A/D input selection register 0 (ADS0) Configuration
Control registers
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Figure 11-1. Block Diagram of 10-Bit A/D Converter
Series resistor string AVDD AVREF P-ch ANI0/P60 ANI1/P61 ANI2/P62 ANI3/P63 ANI4/P64 ANI5/P65 ANI6/P66 Sample & hold circuit
Selector Tap selector
Voltage comparator
AVSS
AVSS
Successive approximation register (SAR)
Controller
INTAD0
3 ADS02 ADS01 ADS00 ADCS0 FR02 FR01 FR00 A/D converter mode register 0 (ADM0) Internal bus
A/D conversion result register 0 (ADCR0)
A/D input selection register 0 (ADS0)
(1)
Successive approximation register (SAR) The SAR receives the result of comparing an analog input voltage and a voltage at a voltage tap (comparison voltage), received from the series resistor string, starting from the most significant bit (MSB). Upon receiving all the bits, down to the least significant bit (LSB), that is, upon the completion of A/D conversion, the SAR sends its contents to A/D conversion result register 0 (ADCR0).
(2)
A/D conversion result register 0 (ADCR0) ADCR0 is a 16-bit register that holds the result of A/D conversion. Lower 6 bits are fixed to 0. Each time A/D conversion ends, the conversion result in the successive approximation register is loaded into ADCR0. The conversion results are stored in ADCR0 starting from the most significant bit (MSB). The higher 8 bits of the conversion results are stored in FF15H and the lower 2 bits of the conversion results are stored in FF14H. ADCR0 is read using a 16-bit memory manipulation instruction. RESET input makes ADCR0 undefined.
Symbol ADCR0
FF15H 0
FF14H 0 0 0 0 0
Address After reset R/W FF14H, Undefined FF15H R
Caution
When the PD78F9418A is used as the flash memory version of the PD789405A, 789406A, and 789407A, 8-bit access is possible, providing an object file has been assembled in the
PD789405A, 789406A, and 789407A.
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(3)
Sample & hold circuit The sample & hold circuit samples consecutive analog inputs from the input circuit, one by one, and sends them to the voltage comparator. The sampled analog input voltage is held during A/D conversion.
(4)
Voltage comparator The voltage comparator compares an analog input with the voltage output by the series resistor string.
(5)
Series resistor string The series resistor string is configured between AVREF and AVSS. against which analog inputs are compared. It generates the reference voltages
(6)
ANI0 to ANI6 pins The ANI0 to ANI6 pins are analog input pins for the seven-channel A/D converter. They are used to receive the analog signals to be subject to A/D conversion. Caution Do not supply the ANI0 to ANI6 pins with voltages that fall outside the rated range. If a voltage greater than AVREF or less than AVSS (even if within the absolute maximum rating) is supplied to any of these pins, the conversion value for the corresponding channel will be undefined. Furthermore, the conversion values for the other channels may also be affected.
(7)
AVREF pin The AVREF pin is a reference voltage pin for the A/D converter. Signals received at the ANI0 to ANI6 pins are converted to digital signals based on the voltage across the AVREF and AVSS pins.
(8)
AVSS pin The AVSS pin is a ground potential pin for the A/D converter. This pin must be held at the same potential as the VSS0 pin, even while the A/D converter is not being used.
(9)
AVDD pin The AVDD pin is an analog power supply pin for the A/D converter. This pin must be held at the same potential as the VDD0 pin, even while the A/D converter is not being used.
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11.3 Registers Controlling 10-Bit A/D Converter
The following two registers are used to control the 10-bit A/D converter. * A/D converter mode register 0 (ADM0) * A/D input selection register 0 (ADS0) (1) A/D converter mode register 0 (ADM0) ADM0 specifies the conversion time for analog inputs. It also specifies whether to enable conversion. ADM0 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADM0 to 00H. Figure 11-2. Format of A/D Converter Mode Register 0
Symbol <7> ADM0 ADCS0 6 0 5 4 3 2 0 1 0 0 0 Address FF80H After reset 00H R/W R/W
FR02 FR01 FR00
ADCS0 0 1 Conversion stopped Conversion enabled
A/D conversion control
FR02 FR01 FR00 0 0 0 1 1 1 0 0 1 0 0 1 0 1 0 0 1 0 144/fx 120/fx 96/fx 72/fx 60/fx 48/fx (28.8 s) (24 s) (19.2 s) (14.4 s)
A/D conversion time selectionNote 1
(Setting prohibitedNote 2) (Setting prohibitedNote 2)
Other than above
Setting prohibited
Notes 1. The specifications of FR02, FR01, and FR00 must be such that the A/D conversion time is at least 14 s. 2. These bit combinations must not be used, as the A/D conversion time will fall below 14 s. Cautions 1. The result of conversion performed immediately after bit 7 (ADCS0) is set is undefined. 2. The result of conversion performed after ADCS0 is cleared may be undefined (see 11.5 (5) Timing that makes the A/D conversion result undefined for details). Remarks 1. fX: Main system clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz.
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(2)
A/D input selection register 0 (ADS0) ADS0 register specifies the port used to input the analog voltages to be converted to a digital signal. ADS0 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADS0 to 00H. Figure 11-3. Format of A/D Input Selection Register 0
Symbol ADS0
7 0
6 0
5 0
4 0
3 0
2
1
0
Address FF84H
After reset 00H
R/W R/W
ADS02 ADS01 ADS00
ADS02 ADS01 ADS00 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 Setting prohibited
Analog input channel specification
Caution
Bits 3 to 7 must be fixed to 0.
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11.4 Operation of 10-Bit A/D Converter
11.4.1 Basic operation of 10-bit A/D converter <1> Select a channel for A/D conversion, using A/D input selection register 0 (ADS0). <2> The voltage supplied to the selected analog input channel is sampled using the sample & hold circuit. <3> After sampling continues for a certain period of time, the sample & hold circuit is put on hold to keep the input analog voltage until A/D conversion is completed. <4> Bit 9 of the successive approximation register (SAR) is set. The series resistor string voltage tap at the tap selector is set to half of AVREF. <5> The series resistor string tap voltage is compared with the analog input voltage using the voltage comparator. If the analog input voltage is higher than half of AVREF, the MSB of the SAR remains set. If it is lower than half of AVREF, the MSB is reset. <6> Bit 8 of the SAR is set automatically, and comparison shifts to the next stage. The next voltage tap of the series resistor string is selected according to bit 9, which reflects the previous comparison result, as follows: * Bit 9 = 1: Three quarters of AVREF * Bit 9 = 0: One quarter of AVREF The tap voltage is compared with the analog input voltage. Bit 8 is set or reset according to the result of comparison. * Analog input voltage tap voltage: Bit 8 = 1 * Analog input voltage < tap voltage: Bit 8 = 0 <7> Comparison is repeated until bit 0 of the SAR is reached. <8> When comparison is completed for all of the 10 bits, a significant digital result is left in the SAR. This value is sent to and latched in A/D conversion result register 0 (ADCR0). At the same time, it is possible to generate an A/D conversion end interrupt request (INTAD0). Cautions 1. The first A/D conversion value immediately following the start of A/D conversion may be undefined. 2. When the A/D converter enters the standby mode, it stops operating.
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Figure 11-4. Basic Operation of 10-Bit A/D Converter
Conversion time
Sampling time A/D converter operation
Sampling
A/D conversion
SAR
Undefined
80H
C0H or 40H
Conversion result
ADCR0
Conversion result
INTAD0
A/D conversion continues until bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) is reset (0) by software. If an attempt is made to write to ADM0 or A/D input selection register 0 (ADS0) during A/D conversion, the current A/D conversion is canceled. In this case, A/D conversion is restarted from the beginning, if the ADCS0 bit is set (1). RESET makes A/D conversion result register 0 (ADCR0) undefined.
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11.4.2 Input voltage and conversion result The relationship between the analog input voltage at the analog input pins (ANI0 to ANI6) and the A/D conversion result (A/D conversion result register 0 (ADCR0)) is represented by: ADCR0 = INT ( or (ADCR0 - 0.5) x AVREF 1024 VIN < (ADCR0 + 0.5) x AVREF 1024 VIN AVREF x 1024 + 0.5)
INT( ): Function that returns the integer part of a parenthesized value VIN: AVREF: Analog input voltage AVREF pin voltage
ADCR0: Value in A/D conversion result register 0 (ADCR0) Figure 11-5 shows the relationship between the analog input voltage and the A/D conversion result. Figure 11-5. Relationship Between Analog Input Voltage and A/D Conversion Result
1023
1022
1021 A/D conversion result (ADCR0) 3
2
1
0 1 3 2 5 3 1 2048 1024 2048 1024 2048 1024 2043 1022 2045 1023 2047 2048 1024 2048 1024 2048 1
Input voltage/AVREF
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11.4.3 Operation mode of 10-bit A/D converter The 10-bit A/D converter is initially in the select mode. In this mode, A/D input selection register 0 (ADS0) is used to select an analog input channel from ANI0 to ANI6 for A/D conversion. A/D conversion can be started only by software, that is, by setting A/D converter mode register 0 (ADM0). The A/D conversion result is saved to A/D conversion result register 0 (ADCR0). At the same time, an interrupt request signal (INTAD0) is generated. * Software-started A/D conversion Setting bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) triggers A/D conversion for a voltage applied to the analog input pin specified in A/D input selection register 0 (ADS0). Upon completion of A/D conversion, the conversion result is saved to A/D conversion result register 0 (ADCR0). At the same time, an interrupt request signal (INTAD0) is generated. Once A/D conversion is activated, and completed, another session of A/D conversion is started. A/D conversion is repeated until new data is written to ADM0. If data where the ADCS0 bit is 1 is written to ADM0 again during A/D conversion, the current session of A/D conversion is discontinued, and a new session of A/D conversion begins for the new data. If data where the ADCS0 bit is 0 is written to ADM0 again during A/D conversion, A/D conversion is stopped immediately. Figure 11-6. Software-Started A/D Conversion
Rewriting ADM0 ADCS0 = 1 Rewriting ADM0 ADCS0 = 1
ADCS0 = 0
A/D conversion
ANIn
ANIn
ANIn
ANIm
ANIm
Conversion is discontinued; no conversion result is preserved.
Stop
ADCR0
ANIn
ANIn
ANIm
INTAD0
Remarks 1. n = 0, 1, ..., 6 2. m = 0, 1, ..., 6
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11.5 Cautions on Using 10-Bit A/D Converter
(1) Current consumption in the standby mode When the A/D converter enters the standby mode, it stops operating. Setting the bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) = 0 can reduce the current consumption. Figure 11-7 shows how to reduce the current consumption in the standby mode. Figure 11-7. How to Reduce Current Consumption in Standby Mode
AVREF
P-ch
ADCS0
Series resistor string AVSS
(2)
Input range for the ANI0 to ANI6 pins Be sure to keep the input voltage at ANI0 to ANI6 within the rated range. If a voltage greater than AVREF or less than AVSS (even within the absolute maximum rating) is input a conversion channel, the conversion output of the channel becomes undefined, and the conversion output of the other channels may be affected.
(3)
Conflict <1> Conflict between writing to A/D conversion result register 0 (ADCR0) at the end of conversion and reading from the ADCR0 bit Reading from the ADCR0 bit takes precedence. After reading, the new conversion result is written to ADCR0 bit. <2> Conflict between writing to the ADCR0 bit at the end of conversion and writing to A/D converter mode register 0 (ADM0) or A/D input selection register 0 (ADS0) Writing to ADM0 or ADS0 takes precedence. A request to write to the ADCR0 bit is ignored. No A/D conversion end interrupt request signal (INTAD0) is generated.
(4)
Conversion results immediately following start of A/D conversion The first A/D conversion value immediately following the start of A/D conversion may be undefined. Be sure to poll the A/D conversion end interrupt request (INTAD0) and perform processing such as discarding the first conversion result.
(5)
Timing that makes the A/D conversion result undefined If the timing of the end of A/D conversion and the timing of the stop of operation of the A/D converter conflict, the A/D conversion value may be undefined. Because of this, be sure to read out the A/D conversion result while the A/D converter is in operation. Furthermore, when reading out an A/D conversion result after A/D conversion has stopped, be sure to have done so by the time the next conversion result is complete. The conversion result readout timing is shown in Figures 11-8 and 11-9.
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Figure 11-8. Conversion Result Readout Timing (When Conversion Result Is Undefined Value)
A/D conversion end A/D conversion end
ADCR0 INTAD0 ADCS0
Normal conversion result
Undefined value
Normal conversion result read out
A/D operation stopped
Undefined value read out
Figure 11-9. Conversion Result Readout Timing (When Conversion Result Is Normal Value)
A/D conversion end
ADCR0 INTAD0 ADCS0
Normal conversion result
A/D operation stopped
Normal conversion result read out
(6)
Noise elimination To maintain a resolution of 10 bits, it is necessary to avoid for noise at the AVREF and ANI0 to ANI6 pins. The higher the output impedance of the analog input source, the larger the effect by noise. To eliminate noise, attach an external capacitor to the relevant pins as shown in Figure 11-10.
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Figure 11-10. Analog Input Pin Processing
If noise greater than AVREF or less than AVSS is likely to come to the AVREF pin, clamp the voltage at the pin by attaching a diode with a small VF (0.3 V or lower).
Reference voltage input
AVREF
C = 100 to 1000 pF
VDD0 AVDD AVSS VSS0
(7)
ANI0 to ANI6 The analog input pins (ANI0 to ANI6) are alternate-function pins. They are also used as port pins (P60 to P66). If any of ANI0 to ANI6 has been selected for A/D conversion, do not execute input instructions for the ports. Otherwise, the conversion resolution may become lower. If a digital pulse is applied to a pin adjacent to the analog input pins during A/D conversion, coupling noise may occur which prevents an A/D conversion result from being attained as expected. Avoid applying a digital pulse to pins adjacent to the analog input pins during A/D conversion.
(8)
Input impedance of ANI0 to ANI6 pins This A/D converter charges the internal sampling capacitor for about 1/10 of the conversion time, and performs sampling. Therefore at times other than sampling, only the leak current is output. During sampling, the current for charging the capacitor is also output, so the input impedance fluctuates and has no meaning. However, to ensure adequate sampling, it is recommended that the output impedance of the analog input source be set to below 10 k, or a 100 pF capacitor be connected to the ANI0 to ANI6 pins (see Figure 1110).
(9)
Input impedance of the AVREF pin A series resistor string of 10 k is connected across the AVREF and AVSS pins. If the output impedance of the reference voltage source is high, this high impedance is eventually connected in parallel with the series resistor string across the AVREF and AVSS pins, leading to a higher reference voltage error.
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(10) Interrupt request flag (ADIF0) Changing the contents of A/D converter mode register 0 (ADM0) does not clear the interrupt request flag (ADIF0). If the voltage at the analog input pins is changed during A/D conversion, therefore, the A/D conversion result and the conversion end interrupt request flag may reflect the previous analog input just before writing to ADM0. In this case, the ADIF0 may appear to be set if it is read-accessed just after ADM0 is writeaccessed, even when A/D conversion has not been completed for the new analog input. In addition, ADIF0 must be cleared before A/D conversion is restarted. Figure 11-11. A/D Conversion End Interrupt Request Generation Timing
Rewriting to ADM0 (to begin conversion for ANIn) Rewriting to ADM0 (to begin conversion for ANIm)
ADIF0 has been set, but conversion for ANIm has not been completed.
A/D conversion
ANIn
ANIn
ANIm
ANIm
ADCR0
ANIn
ANIn
ANIm
ANIm
INTAD0
Remarks 1. n = 0, 1, ..., 6 2. m = 0, 1, ..., 6 (11) AVDD pin The AVDD pin is used to supply power to the analog circuit. It is also used to supply power to the ANI0 to ANI6 input circuit. If your application is designed to be changed to backup power, the AVDD pin must be supplied with the same voltage level as for the VDD0 pin, as shown in Figure 11-12. Figure 11-12. AVDD Pin Processing
VDD0 AVDD Main power source Backup capacitor VSS0 AVSS
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CHAPTER 12 COMPARATOR
12.1 Functions of Comparator
The comparator has the following functions. (1) Input voltage comparison by comparator The comparator compares an input voltage at the reference voltage input pin (CMPREF0) with an input voltage at the comparator input pin (CMPIN0). manipulation instructions. (2) Interrupt generation by comparator output The comparator output is used to generate an interrupt request signal
Note
The comparison result can be read using memory
(INTCMP0).
Note The rising edge, falling edge, or both rising and falling edges can be specified by setting external interrupt mode register 1 (INTM1). (3) Clock output When CMPREF0 > CMPIN0, the output of 8-bit timer counter 02 (TM02) is directed to the CMPTOUT0 pin. (4) Open-drain output selection Comparator mode register 0 (CMPRM0) is used to specify a port as an N-ch open-drain output.
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12.2 Configuration of Comparator
The comparator consists of the following hardware. (1) CMPIN0 This is the comparator input pin. (2) CMPTOUT0 This is the comparator output pin. (3) CMPREF0 This is the comparator reference voltage input pin. Figure 12-1 is a block diagram of the comparator. Figure 12-1. Block Diagram of Comparator
Internal bus
P23 output latch
PM23
CMPIN0 CMPREF0
_ +
Timing control
Selector
8-bit timer 02 (TM02) output
CMPTOUT0/P23/ TO2
Edge selector
INTCMP0
ES61
ES60
CMPON0
SELCMP0
OPDR0
CMPOUT0
External interrupt mode register 1 (INTM1) Internal bus
Comparator mode register 0 (CMPRM0)
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12.3 Register Controlling Comparator
The comparator is controlled by the following register. (1) Comparator mode register 0 (CMPRM0) CMPRM0 controls the power supply and clock output of the comparator. It also selects an open-drain output for the comparator. CMPRM0 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets CMPRM0 to 00H. Figure 12-2. Format of Comparator Mode Register 0
Symbol CMPRM0 7 0 6 0 5 0 4 0 3 2 1 0 Address FF4EH After reset 00H R/W R/WNote
CMPON0 SELCMP0 OPDR0 CMPOUT0
CMPON0 0 1 Comparator power supply off Comparator power supply on
Comparator power supply on/off control
SELCMP0 0 1 8-bit timer 02 (TM02) output
Clock output control
8-bit timer counter 02 (TM02) output if CMPREF0 > CMPIN0
OPDR0 0 1 CMOS output N-ch open-drain output
Open-drain output selection
CMPOUT0 The comparator output is read.
Note Bit 0 is read-only. Cautions 1. Bits 4 to 7 must be fixed to 0. 2. If the comparator is enabled (CMPON0 = 1), noise may be induced. If it is necessary to generate an interrupt request signal (INTCMP0) from the output of the comparator, enable the comparator (CMPON0 = 1), then clear the interrupt request flag (CMPIF0) to 0, before enabling interrupts. 3. Similarly, if it is necessary to direct the output of the comparator to the port, enable the comparator (CMPON0 = 1) in advance.
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12.4 Operation of Comparator
The output of 8-bit timer 02 (TM02) can be controlled and directed to the CMPTOUT0/P23/TO2 pin via the comparator. To run the comparator, set as follows: * Set P23 to output mode (PM23 = 0). * Set comparator mode register 0 (CMPRM0) as shown in Figure 12-3. * Set external interrupt mode register 1 (INTM1) as shown in Figure 12-4 and select the valid edge of INTCMP0. Figure 12-3. Settings of Comparator Mode Register 0 for Comparator Operation
CMPON0 SELCMP0 CMPRM0 0 0 0 0 1 1 OPDR0 0/1 CMPOUT0 -
Outputs TM02. Switches on the comparator power.
Figure 12-4. Settings of External Interrupt Mode Register 1 at INTCMP0 Occurrence
ES61 INTM1 0/1 ES60 0/1 0 0 1 1 ES31 0/1 ES30 0/1
Selects the valid edge (see Table 12-1).
Table 12-1 lists the selection of INTCMP0 valid edges, and Figure 12-5 shows the timing chart of the comparator. Table 12-1. INTCMP0 Valid Edges
ES61 0 0 1 1 ES60 0 1 0 1 Falling edge Rising edge Setting prohibited Both rising and falling edges INTCMP0 Valid Edge Selection
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Figure 12-5. Comparator Operation Timing (1/2)
Timer (TM02) output
CMPOUT0
CMPTOUT0
SELCMP0
Timer (TM02) output enable signal
<1> CMPOUT0 is latched on the rising edge of the TM02 output to generate a signal to enable output to the CMPTOUT0/P23/TO2 pin. output. <2> If SELCMP0 is low, the TM02 output is sent to the CMPTOUT0/P23/TO2 pin no matter which level CMPOUT0 is on. Figure 12-5. Comparator Operation Timing (2/2)
Timer (TM02) output
If CMPOUT0 is high, the TM02 output waveform is output to the
CMPTOUT0/P23/TO2 pin on the rising edge of the TM02 output. If CMPOUT0 is low, CMPTOUT0 is not
CMPOUT0
CMPTOUT0
SELCMP0
Timer (TM02) output enable signal
<3> If the high level of CMPOUT0 is latched on the rising edge of the TM02 output, CMPTOUT0 is output to the CMPTOUT0/P23/TO2 pin for at least two clock pulses even if it falls immediately. <4> Switching SELCMP0 from high to low during CMPTOUT0 output may disturb the output waveform of CMPTOUT0.
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13.1 Functions of Serial Interface 00
Serial interface 00 has the following three modes. * Operation stopped mode * Asynchronous serial interface (UART) mode * 3-wire serial I/O mode (1) Operation stopped mode This mode is used to reduce power consumption when serial transfer is not carried out. (2) Asynchronous serial interface (UART) mode In this mode, one byte of data following the start bit is transmitted/received, and full-duplex operation is possible. A dedicated UART baud rate generator is incorporated, allowing communication over a wide range of baud rates. In addition, the baud rate can be defined by dividing the clock input to the ASCK pin. (3) 3-wire serial I/O mode (MSB/LSB start bit switchable) In this mode, 8-bit data transfer is carried out using three lines, one for the serial clock (SCK) and two for serial data (SI, SO). The 3-wire serial I/O mode supports simultaneous transmit and receive operations, reducing data transfer processing time. It is possible to switch the start bit of 8-bit data to be transmitted between the MSB and the LSB, thus allowing connection to devices with either start bit. The 3-wire serial I/O mode is effective for connecting display controllers and peripheral I/Os such as the 75XL Series, 78K Series, and 17K Series, which have conventional clock synchronous serial interfaces.
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13.2 Configuration of Serial Interface 00
Serial interface 00 consists of the following hardware. Table 13-1. Configuration of Serial Interface 00
Item Registers Transmit shift register 00 (TXS00) Receive shift register 00 (RXS00) Receive buffer register 00 (RXB00) Serial operation mode register 00 (CSIM00) Asynchronous serial interface mode register 00 (ASIM00) Asynchronous serial interface status register 00 (ASIS00) Baud rate generator control register 00 (BRGC00) Configuration
Control registers
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Figure 13-1. Block Diagram of Serial Interface 00
Internal bus Asynchronous serial interface status register 00 (ASIS00) Receive buffer register 00 (RXB00/SIO00) PE00 FE00 OVE00 Asynchronous serial interface mode register 00 (ASIM00) TXE00 RXE00 PS001 PS000 CL00 SL00
Direction controller
Direction controller
Transmit shift register 00 (TXS00/SIO00)
CHAPTER 13 SERIAL INTERFACE 00
RxD/SI/P22 TxD/SO/P21 PM21
Receive shift register 00 (RXS00)
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SCK output controller PM20 ASCK/SCK/P20
Note
Receive controller
INTSR00/INTCSI00
Transmit controller
INTST00
Baud rate generator fX/2 to fX/28 CSIE00 TXE00 RXE00 CSIE00 DIR00 CSCK00 Serial operation mode register 00 (CSIM00) Internal bus 4 CSCK00
TPS003 TPS002 TPS001 TPS000 Baud rate generator control register 00 (BRGC00)
173
Note
For the baud rate generator configuration, see Figure 13-2.
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Clear Transmit clock
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Selector
Selector
1/2 Clear
Selector
174
BRGC00 write TXE00 1/2 Receive clock CSCK00 CSIE00 RXE00 CSIE00 Start bit detection BRGC00 write RXE00
Figure 13-2. Block Diagram of Baud Rate Generator
CSIE00 TXE00 RXE00
Stop Prescaler fX 28 Clear fX 27 fX 26 fX 25 fX 24 fX 23 fX 22 fX 2
CHAPTER 13 SERIAL INTERFACE 00
3-bit counter
ASCK/SCK/P20
4 3-bit counter Clear
TPS003 TPS002 TPS001 TPS000 Baud rate generator control register 00 (BRGC00) Internal bus
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CHAPTER 13 SERIAL INTERFACE 00
(1)
Transmit shift register 00 (TXS00) This register is used to specify data to be transmitted. Data written to TXS00 is transmitted as serial data. If the data length is specified as 7 bits, bits 0 to 6 of the data written to TXS00 are transferred as the transmit data. The transmit operation is started by writing data to TXS00. TXS00 is written to using an 8-bit memory manipulation instruction. It cannot be read. RESET input sets TXS00 to FFH. Caution Do not write to TXS00 during a transmit operation. TXS00 and receive buffer register 00 (RXB00) are allocated to the same address, and when reading is performed, RXB00 values are read.
(2)
Receive shift register 00 (RXS00) This register is used to convert serial data input to the RxD pin into parallel data. Each time one byte of data is received, it is transferred to receive buffer register 00 (RXB00). RXS00 cannot be manipulated directly by program.
(3)
Receive buffer register 00 (RXB00) This register is used to hold received data. Each time one byte of data is received, a new byte of data is transferred from receive shift register 00 (RXS00). If the data length is specified as 7 bits, receive data is transferred to bits 0 to 6 of RXB00, and the MSB of RXB00 always becomes 0. RXB00 can be read using an 8-bit memory manipulation instruction. It cannot be written to. RESET input makes RXB00 undefined. Caution RXB00 and transmit shift register 00 (TXS00) are allocated to the same address, and when writing is performed, the values are written to TXS00.
(4)
Transmit controller This circuit controls transmit operations by adding a start bit, parity bit, and stop bit to data written to transmit shift register 00 (TXS00), according to the data set to asynchronous serial interface mode register 00 (ASIM00).
(5)
Receive controller This circuit controls receive operations according to the data set to asynchronous serial interface mode register 00 (ASIM00). It also performs a parity error check, etc., during receive operations, and when an error is detected, it sets a value to asynchronous serial interface status register 00 (ASIS00) in accordance with the nature of the error.
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13.3 Registers Controlling Serial Interface 00
The following four registers are used to control serial interface 00. * Serial operation mode register 00 (CSIM00) * Asynchronous serial interface mode register 00 (ASIM00) * Asynchronous serial interface status register 00 (ASIS00) * Baud rate generator control register 00 (BRGC00) (1) Serial operation mode register 00 (CSIM00) This register is set when using serial interface 00 in the 3-wire serial I/O mode. CSIM00 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM00 to 00H. Figure 13-3. Format of Serial Operation Mode Register 00
Symbol <7> 6 0 5 0 4 0 3 0 2 1 0 0 Address FF72H After reset 00H R/W R/W
CSIM00 CSIE00
DIR00 CSCK00
CSIE00 0 1 Operation stopped Operation enabled
Operation control in 3-wire serial I/O mode
DIR00 0 1 MSB LSB
Start bit specification
CSCK00 0 1
Clock selection in 3-wire serial I/O mode Clock input to SCK pin from external Dedicated baud rate generator output
Cautions 1. Bits 0 and 3 to 6 must be fixed to 0. 2. Set CSIM00 to 00H in the UART mode.
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(2)
Asynchronous serial interface mode register 00 (ASIM00) This register is set when using serial interface 00 in the asynchronous serial interface mode. ASIM00 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM00 to 00H. Figure 13-4. Format of Asynchronous Serial Interface Mode Register 00
Symbol ASIM00
<7>
<6>
5
4
3
2
1 0
0 0
Address FF70H
After reset 00H
R/W R/W
TXE00 RXE00 PS001 PS000 CL00 SL00
TXE00 0 1 Transmit operation stopped Transmit operation enabled
Transmit operation control
RXE00 0 1 Receive operation stopped Receive operation enabled
Receive operation control
PS001 PS000 0 0 0 1 No parity
Parity bit specification
0 parity always added at transmission Parity check is not performed at reception (no parity error occurs) Odd parity Even parity
1 1
0 1
CL00 0 1 7 bits 8 bits
Character length specification
SL00 0 1 1 bit 2 bits
Transmit data stop bit length specification
Cautions 1. Bits 0 and 1 must be fixed to 0. 2. Set ASIM00 to 00H in the 3-wire serial I/O mode. 3. Switching operation modes must be performed after the serial transmit/receive operation is stopped.
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Table 13-2. Operation Mode Settings of Serial Interface 00 (1) Operation stopped mode
CSIM00 PM22 P22 PM21 P21 PM20 P20 Start Bit x Note 1 x Note 1 x Note 1 x Note 1 x Note 1 x Note 1 -- Shift Clock -- P22/SI/RxD Pin Function P22 P21/SO/TxD Pin Function P21 P20/SCK/ASCK Pin Function P20
ASIM00
TXE00 RXE00 CSIE00 DIR00 CSCK00 0 0 0 x x
Other than above
Setting prohibited
(2)
Asynchronous serial interface mode
CSIM00 PM22 P22 PM21 P21 PM20 P20 Start Bit x Note 1 x Note 1 0 1 1 x LSB Shift Clock External clock x Note 1 x Note 1 Internal clock P22/SI/RxD Pin Function P22 P21/SO/TxD Pin Function TxD (CMOS output) P20 P20/SCK/ASCK Pin Function ASCK input
ASIM00
TXE00 RXE00 CSIE00 DIR00 CSCK00 1 0 0 0 0
0
1
0
0
0
1
x
x Note 1 x Note 1
1
x
External clock
RxD
P21
ASCK input
x Note 1 x Note 1
Internal clock
P20
1
1
0
0
0
1
x
0
1
1
x
External clock
TxD (CMOS output)
ASCK input
x Note 1 x Note 1
Internal clock
P20
Other than above
Setting prohibited
(3)
3-wire serial I/O mode
CSIM00 PM22 P22 PM21 P21 PM20 P20 Start Bit 1Note 2 x Note 2 0 1 1 x Shift Clock P22/SI/RxD Pin Function SI Note 2 P21/SO/TxD Pin Function SO (CMOS output) SCK output P20/SCK/ASCK Pin Function SCK input
ASIM00
TXE00 RXE00 CSIE00 DIR00 CSCK00 0 0 1 0 0
MSB External clock
1
0
1
Internal clock
1
1
0
1
x
LSB
External clock
SCK input
1
0
1
Internal clock
SCK output
Other than above
Setting prohibited
Notes 1. Can be used as port function. 2. If used only for transmission, can be used as P22 (CMOS I/O). Remark x: Don't care
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(3)
Asynchronous serial interface status register 00 (ASIS00) This register indicates the type of error when a reception error occurs in the asynchronous serial interface mode. ASIS00 is read using a 1-bit or 8-bit memory manipulation instruction. The contents of ASIS00 become undefined in the 3-wire serial I/O mode. RESET input sets ASIS00 to 00H. Figure 13-5. Format of Asynchronous Serial Interface Status Register 00
Symbol ASIS00
7 0
6 0
5 0
4 0
3 0
2
1
0
Address FF71H
After reset 00H
R/W R
PE00 FE00 OVE00
PE00 0 1 Parity error did not occur
Parity error flag
Parity error occurred (when the transmit parity and receive parity did not match)
FE00 0 1 Framing error did not occur
Framing error flag
Framing error occurred (when stop bit was not detected)Note 1
OVE00 0 1 Overrun error did not occur
Overrun error flag
Overrun error occurredNote 2 (when the next receive operation was completed before the data was read from receive buffer register 00)
Notes 1. Even when the stop bit length is set to 2 bits by setting bit 2 (SL00) of asynchronous serial interface mode register 00 (ASIM00), only one stop bit is detected during reception. 2. Be sure to read receive buffer register 00 (RXB00) when an overrun error occurs. If not, an overrun error will occur every time the data is received.
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(4)
Baud rate generator control register 00 (BRGC00) This register is used to set the serial clock of serial interface 00. BRGC00 is set using an 8-bit memory manipulation instruction. RESET input sets BRGC00 to 00H. Figure 13-6. Format of Baud Rate Generator Control Register 00
Symbol
7
6
5
4
3 0
2 0
1 0
0 0
Address FF73H
After reset 00H
R/W R/W
BRGC00 TPS003 TPS002 TPS001 TPS000
TPS003 TPS002 TPS001 TPS000 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 fX/2 (2.5 MHz) fX/2 (1.25 MHz) fX/23 (625 kHz) fX/24 (313 kHz) fX/2 (156 kHz) fX/2 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz)
6 5 2
3-bit counter source clock selection
n 1 2 3 4 5 6 7 8
Clock input from external to ASCK pin Setting prohibited
Note
-
Other than above
Note Only used in the UART mode. Cautions 1. When BRGC00 is written during a communication operation, the output of the baud rate generator is disrupted and communications cannot be performed normally. Be sure not to write to BRGC00 during a communication operation. 2. Do not select n = 1 during fX = 5.0 MHz operation because the baud rate rating is exceeded. Remarks 1. fX: Main system clock oscillation frequency 2. n: Value determined in the settings of TPS000 to TPS003 (1 n 8) 3. The parenthesized values apply to operation at fX = 5.0 MHz.
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The baud rate transmit/receive clock to be generated is either a signal divided from the main system clock, or a signal divided from the clock input from the ASCK pin. (a) Generation of baud rate transmit/receive clock from main system clock The transmit/receive clock is generated by dividing the main system clock. The baud rate generated from the main system clock is estimated by using the following expression. [Baud rate] = fX 2
n+1
x8
[Hz]
fX: Main system clock oscillation frequency n: Value in Figure 13-6 that is determined in the settings of TPS000 to TPS003 (2 n 8) Table 13-3. Example of Relationship Between Main System Clock and Baud Rate
Baud Rate (bps) 1200 2400 4800 9600 19200 38400 76800 70H 60H 50H 40H 30H 20H 10H BRGC00 Set Value fX = 5.0 MHz 1.73 Error (%) fX = 4.9152 MHz 0
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(b)
Generation of baud rate transmit/receive clock from external clock of ASCK pin The transmit/receive clock is generated by dividing the clock input from the ASCK pin. The baud rate generated from the clock input from the ASCK pin is estimated by using the following expression. [Baud rate] = fASCK 16 [Hz]
fASCK: Frequency of clock input to the ASCK pin Table 13-4. Relationship Between ASCK Pin Input Frequency and Baud Rate (When BRGC00 Is Set to 80H)
Baud Rate (bps) 75 150 300 600 1200 2400 4800 9600 19200 31250 38400 ASCK Pin Input Frequency (kHz) 1.2 2.4 4.8 9.6 19.2 38.4 76.8 153.6 307.2 500.0 614.4
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13.4 Operation of Serial Interface 00
Serial interface 00 has the following three modes. * Operation stopped mode * Asynchronous serial interface (UART) mode * 3-wire serial I/O mode 13.4.1 Operation stopped mode Serial transfer is not executed in the operation stopped mode, therefore the power consumption can be reduced. The P20/SCK/ASCK, P21/SO/TxD, and P22/SI/RxD pins can be used as normal I/O port pins. (1) Register setting Operation stopped mode is set by serial operation mode register 00 (CSIM00) and asynchronous serial interface mode register 00 (ASIM00). (a) Serial operation mode register 00 (CSIM00) CSIM00 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM00 to 00H.
Symbol <7> 6 0 5 0 4 0 3 0 2 1 0 0 Address FF72H After reset 00H R/W R/W
CSIM00 CSIE00
DIR00 CSCK00
CSIE00 0 1 Operation stopped Operation enabled
Operation control in 3-wire serial I/O mode
Caution Bits 0 and 3 to 6 must be fixed to 0.
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(b)
Asynchronous serial interface mode register 00 (ASIM00) ASIM00 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM00 to 00H.
Symbol ASIM00
<7>
<6>
5
4
3
2
1 0
0 0
Address FF70H
After reset 00H
R/W R/W
TXE00 RXE00 PS001 PS000 CL00 SL00
TXE00 0 1 Transmit operation stopped Transmit operation enabled
Transmit operation control
RXE00 0 1 Receive operation stopped Receive operation enabled
Receive operation control
Caution Bits 0 and 1 must be fixed to 0.
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13.4.2 Asynchronous serial interface (UART) mode In this mode, the one-byte data following the start bit is transmitted/received and thus full-duplex communications are possible. This device incorporates a UART-dedicated baud rate generator, enabling communication at the desired baud rate. In addition, the baud rate can also be defined by dividing the clock input to the ASCK pin. The UART-dedicated baud rate generator can also output a 31.25 kbps baud rate, which complies with the MIDI standard. (1) Register setting UART mode is set by serial operation mode register 00 (CSIM00), asynchronous serial interface mode register 00 (ASIM00), asynchronous serial interface status register 00 (ASIS00), and baud rate generator control register 00 (BRGC00). (a) Serial operation mode register 00 (CSIM00) CSIM00 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM00 to 00H. Set CSIM00 to 00H in the UART mode.
Symbol CSIM00 <7> CSIE00 6 0 5 0 4 0 3 0 2 1 0 0 Address FF72H After reset 00H R/W R/W
DIR00 CSCK00
CSIE00 0 1 Operation stopped Operation enabled
Operation control in 3-wire serial I/O mode
DIR00 0 1 MSB LSB
Start bit specification
CSCK00 0 1
Clock selection in 3-wire serial I/O mode Clock input to SCK pin from external Dedicated baud rate generator output
Caution Bits 0 and 3 to 6 must be fixed to 0.
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(b)
Asynchronous serial interface mode register 00 (ASIM00) ASIM00 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM00 to 00H.
Symbol ASIM00
<7>
<6>
5
4
3
2
1 0
0 0
Address FF70H
After reset 00H
R/W R/W
TXE00 RXE00 PS001 PS000 CL00 SL00
TXE00 0 1 Transmit operation stopped Transmit operation enabled
Transmit operation control
RXE00 0 1 Receive operation stopped Receive operation enabled
Receive operation control
PS001 PS000 0 0 0 1 No parity
Parity bit specification
0 parity always added at transmission Parity check is not performed at reception (no parity error occurs) Odd parity Even parity
1 1
0 1
CL00 0 1 7 bits 8 bits
Character length specification
SL00 0 1 1 bit 2 bits
Transmit data stop bit length specification
Cautions 1. Bits 0 and 1 must be fixed to 0. 2. Switching operation modes must be performed after the serial transmit/receive operation is stopped.
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(c)
Asynchronous serial interface status register 00 (ASIS00) ASIS00 is read using a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIS00 to 00H.
Symbol ASIS00
7 0
6 0
5 0
4 0
3 0
2
1
0
Address FF71H
After reset 00H
R/W R
PE00 FE00 OVE00
PE00 0 1 Parity error did not occur
Parity error flag
Parity error occurred (when the transmit parity and receive parity did not match)
FE00 0 1 Framing error did not occur
Framing error flag
Framing error occurred (when stop bit was not detected)Note 1
OVE00 0 1 Overrun error did not occur
Overrun error flag
Overrun error occurredNote 2 (when the next receive operation was completed before the data was read from receive buffer register 00)
Notes 1. Even when the stop bit length is set to 2 bits by setting bit 2 (SL00) of asynchronous serial interface mode register 00 (ASIM00), only one stop bit will be detected during reception. 2. Be sure to read receive buffer register 00 (RXB00) when an overrun error occurs. If not, every time the data is received an overrun error occurs.
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(d)
Baud rate generator control register 00 (BRGC00) BRGC00 is set using an 8-bit memory manipulation instruction. RESET input sets BRGC00 to 00H.
Symbol
7
6
5
4
3 0
2 0
1 0
0 0
Address FF73H
After reset 00H
R/W R/W
BRGC00 TPS003 TPS002 TPS001 TPS000
TPS003 TPS002 TPS001 TPS000 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 fX/2 (2.5 MHz) fX/22 (1.25 MHz) fX/2 (625 kHz) fX/2 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/2 (39.1 kHz) fX/2 (19.5 kHz)
8 7 4 3
3-bit counter source clock selection
n 1 2 3 4 5 6 7 8
Clock input from external to ASCK pin Setting prohibited
Other than above
Cautions 1. When BRGC00 is written during a communication operation, the output of the baud rate generator is disrupted and communications cannot be performed normally. Be sure not to write to BRGC00 during a communication operation. 2. Do not select n = 1 during fX = 5.0 MHz operation because the baud rate rating is exceeded. Remarks 1. fX: Main system clock oscillation frequency 2. n: Value determined in the settings of TPS000 to TPS003 (1 n 8) 3. The parenthesized values apply to operation at fX = 5.0 MHz.
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The baud rate transmit/receive clock to be generated is either a signal divided from the main system clock, or a signal divided from the clock input from the ASCK pin. (i) Generation of baud rate transmit/receive clock from main system clock The transmit/receive clock is generated by dividing the main system clock. The baud rate generated from the main system clock is estimated by using the following expression. [Baud rate] = fX 2
n+1
x8
[Hz]
fX: Main system clock oscillation frequency n: Value in the above table that is determined in the settings of TPS000 to TPS003 (2 n 8) Table 13-5. Example of Relationship Between Main System Clock and Baud Rate
Baud Rate (bps) 1200 2400 4800 9600 19200 38400 76800 70H 60H 50H 40H 30H 20H 10H BRGC00 Set Value fX = 5.0 MHz 1.73 Error (%) fX = 4.9152 MHz 0
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(ii)
Generation of baud rate transmit/receive clock from external clock of ASCK pin The transmit/receive clock is generated by dividing the clock input from the ASCK pin. The baud rate generated from the clock input from the ASCK pin is estimated by using the following expression. [Baud rate] = fASCK 16 [Hz]
fASCK: Frequency of clock input to the ASCK pin Table 13-6. Relationship Between ASCK Pin Input Frequency and Baud Rate (When BRGC00 Is Set to 80H)
Baud Rate (bps) 75 150 300 600 1200 2400 4800 9600 19200 31250 38400 ASCK Pin Input Frequency (kHz) 1.2 2.4 4.8 9.6 19.2 38.4 76.8 153.6 307.2 500.0 614.4
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(2)
Communication operation (a) Data format The transmit/receive data format is as shown in Figure 13-7. One data frame consists of a start bit, character bits, parity bit and stop bit(s). The specification of character bit length, parity selection, and specification of stop bit length for each data frame is carried out using asynchronous serial interface mode register 00 (ASIM00). Figure 13-7. Format of Asynchronous Serial Interface Transmit/Receive Data
One data frame
Start bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity bit
Stop bit
* Start bit ...................... * Character bits............. * Parity bits ................... * Stop bit(s)...................
1 bit 7 bits/8 bits Even parity/odd parity/0 parity/no parity 1 bit/2 bits
When 7 bits are selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid; the most significant bit (bit 7) is ignored in transmission, and the most significant bit (bit 7) is always 0 in reception. The serial transfer rate is selected using ASIM00 and baud rate generator control register 00 (BRGC00). If a serial data receive error occurs, the receive error contents can be determined by reading the status of asynchronous serial interface status register 00 (ASIS00).
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(b)
Parity types and operation The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit is used on the transmitting side and the receiving side. With even parity and odd parity, a "1" bit (odd number) error can be detected. With 0 parity and no parity, an error cannot be detected. (i) Even parity * At transmission The transmission operation is controlled so that the number of bits with a value of 1 in the transmit data including the parity bit may be even. The parity bit value should be as follows. The number of bits with a value of 1 is an odd number in transmit data: The number of bits with a value of 1 is an even number in transmit data: * At reception The number of bits with a value of 1 in the receive data including the parity bit is counted, and if the number is odd, a parity error occurs. (ii) Odd parity * At transmission Conversely to even parity, the transmission operation is controlled so that the number of bits with a value of 1 in the transmit data including the parity bit may be odd. The parity bit value should be as follows. The number of bits with a value of 1 is an odd number in transmit data: The number of bits with a value of 1 is an even number in transmit data: * At reception The number of bits with a value of 1 in the receive data including the parity bit is counted, and if the number is even, a parity error occurs. (iii) 0 Parity When transmitting, the parity bit is set to 0 irrespective of the transmit data. At reception, a parity bit check is not performed. irrespective of whether the parity bit is set to 0 or 1. (iv) No parity A parity bit is not added to the transmit data. At reception, data is received assuming that there is no parity bit. Since there is no parity bit, a parity error does not occur. Therefore, a parity error does not occur, 0 1 1 0
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(c)
Transmission A transmit operation is started by writing transmit data to transmit shift register 00 (TXS00). The start bit, parity bit and stop bit(s) are added automatically. When the transmit operation starts, the data in TXS00 is shifted out, and when TXS00 is empty, a transmission completion interrupt (INTST00) is generated. Figure 13-8. Asynchronous Serial Interface Transmission Completion Interrupt Timing (a) Stop bit length: 1
Stop
TxD (Output) Start INTST00
D0
D1
D2
D6
D7
Parity
(b) Stop bit length: 2
TxD (Output) Start INTST00
D0
D1
D2
D6
D7
Parity
Stop
Caution Do not rewrite asynchronous serial interface mode register 00 (ASIM00) during a transmit operation. If ASIM00 is rewritten during transmission, subsequent transmission may not operate correctly (the normal state is restored by RESET input). Whether transmission is in progress or not can be judged by software using a transmission completion interrupt (INTST00) or the interrupt request flag (STIF00) set by INTST00.
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(d)
Reception When bit 6 (RXE00) of asynchronous serial interface mode register 00 (ASIM00) is set (1), a receive operation is enabled and sampling of the RxD pin input is performed. RxD pin input sampling is performed using the serial clock specified by ASIM00. When the RxD pin input becomes low, the 3-bit counter starts counting, and when half the time determined by the specified baud rate has passed, the data sampling start timing signal is output. If the RxD pin input sampled again as a result of this start timing signal is low, it is identified as a start bit, the 3-bit counter is initialized and starts counting, and data sampling is performed. When character data, a parity bit and one stop bit are detected after the start bit, reception of one frame of data ends. When one frame of data has been received, the receive data in the shift register is transferred to receive buffer register 00 (RXB00), and a reception completion interrupt (INTSR00) is generated. If an error occurs, the receive data in which the error occurred is still transferred to RXB00, and INTSR00 is generated. If the RXE00 bit is reset (0) during the receive operation, the receive operation is stopped immediately. In this case, the contents of RXB00 and asynchronous serial interface status register 00 (ASIS00) are not changed, and INTSR00 is not generated. Figure 13-9. Asynchronous Serial Interface Reception Completion Interrupt Timing
Stop
RxD (Input) Start INTSR00
D0
D1
D2
D6
D7
Parity
Caution Be sure to read receive buffer register 00 (RXB00) even if a receive error occurs. If RXB00 is not read, an overrun error will occur when the next data is received, and the receive error state will continue indefinitely.
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(e)
Receive errors The following three errors may occur during a receive operation: a parity error, framing error, or overrun error. The data reception result error flag is set in asynchronous serial interface status register 00 (ASIS00). Receive error causes are shown in Table 13-7. What kind of error occurred during reception can be judged by reading the contents of ASIS00 in the receive error interrupt servicing (see Figures 13-9 and 13-10). The contents of ASIS00 are reset (0) by reading receive buffer register 00 (RXB00) or receiving the next data (if there is an error in the next data, the corresponding error flag is set). Table 13-7. Receive Error Causes
Receive Errors Parity error Framing error Overrun error
Cause The parity specified at transmission and the reception data parity do not match. A stop bit is not detected. Reception of the next data is completed before data is read from the receive buffer register.
Figure 13-10. Receive Error Timing (a) Parity error occurs
Stop RxD (input) Start INTSR00 D0 D1 D2 D6 D7 Parity
(b) Framing error or overrun error occurs
Stop RxD (input) Start INTSR00 D0 D1 D2 D6 D7 Parity
Cautions 1. The contents of the ASIS00 register are reset (0) by reading receive buffer register 00 (RXB00) or receiving the next data. ASIS00 before reading RXB00. 2. Be sure to read receive buffer register 00 (RXB00) even if a receive error occurs. If RXB00 is not read, an overrun error will occur when the next data is received, and the receive error state will continue indefinitely. To ascertain the error contents, read
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(f)
Reading receive data When the reception completion interrupt (INTSR00) is generated, receive data can be read by reading the value of receive buffer register 00 (RXB00). To read the receive data stored in receive buffer register 00 (RXB00), read while reception is enabled (RXE00 = 1). Remark However, if it is necessary to read receive data after reception has stopped (RXE00 = 0), read using either of the following methods. (a) (b) Read after setting RXE00 = 0 after waiting for one cycle or more of the source clock selected by BRGC00. Read after bit 2 (DIR00) of serial operation mode register 00 (CSIM00) is set (1).
Program example of (a) (BRGC00 = 00H (source clock = fx/2)) INTRXE: NOP CLR1 RXE00 MOV A, RXB00 ; ;2 clocks ;Reception stopped ;Read receive data
Program example of (b) INTRXE: SET1 CSIM00.2 CLR1 RXE00 MOV A, RXB00 ; ;DIR00 flag is set to LSB first ;Reception stopped ;Read receive data
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(3)
Cautions on UART mode (a) When bit 7 (TXE00) of asynchronous serial interface mode register 00 (ASIM00) is cleared during transmission, be sure to set transmit shift register 00 (TXS00) to FFH, then set the TXE00 bit to 1 before executing the next transmission. (b) When bit 6 (RXE00) of asynchronous serial interface mode register 00 (ASIM00) is cleared during reception, receive buffer register 00 (RXB00) and the reception completion interrupt (INTSR00) are as follows.
RxD pin
Parity
RXB00
INTSR00
<1>
<3> <2>
When RXE00 is set to 0 at the timing indicated by <1>, RXB00 holds the previous data and does not generate INTSR00. When RXE00 is set to 0 at the timing indicated by <2>, RXB00 renews the data and does not generate INTSR00. When RXE00 is set to 0 at the timing indicated by <3>, RXB00 renews the data and generates INTSR00.
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13.4.3 3-wire serial I/O mode The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which incorporate a conventional synchronous serial interface, such as the 75XL Series, 78K Series, and 17K Series. Communication is performed using three lines: the serial clock (SCK), serial output (SO), and serial input (SI). (1) Register setting 3-wire serial I/O mode settings are performed using serial operation mode register 00 (CSIM00), asynchronous serial interface mode register 00 (ASIM00), and baud rate generator control register 00 (BRGC00). (a) Serial operation mode register 00 (CSIM00) CSIM00 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM00 to 00H.
Symbol <7> 6 0 5 0 4 0 3 0 2 1 0 0 Address FF72H After reset 00H R/W R/W
CSIM00 CSIE00
DIR00 CSCK00
CSIE00 0 1 Operation stopped Operation enabled
Operation control in 3-wire serial I/O mode
DIR00 0 1 MSB LSB
Start bit specification
CSCK00 0 1
Clock selection in 3-wire serial I/O mode Clock input to SCK pin from external Dedicated baud rate generator output
Caution Bits 0 and 3 to 6 must be fixed to 0.
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(b)
Asynchronous serial interface mode register 00 (ASIM00) ASIM00 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM00 to 00H. ASIM00 must be set to 00H in the 3-wire serial I/O mode.
Symbol ASIM00
<7>
<6>
5
4
3
2
1 0
0 0
Address FF70H
After reset 00H
R/W R/W
TXE00 RXE00 PS001 PS000 CL00 SL00
TXE00 0 1 Transmit operation stopped Transmit operation enabled
Transmit operation control
RXE00 0 1 Receive operation stopped Receive operation enabled
Receive operation control
PS001 PS000 0 0 0 1 No parity
Parity bit specification
0 parity always added at transmission Parity check is not performed at reception (no parity error occurs.) Odd parity Even parity
1 1
0 1
CL00 0 1 7 bits 8 bits
Character length specification
SL00 0 1 1 bit 2 bits
Transmit data stop bit length specification
Cautions 1. Bits 0 and 1 must be fixed to 0. 2. Switching operation modes must be performed after the serial transmit/receive operation is stopped.
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(c)
Baud rate generator control register 00 (BRGC00) BRGC00 is set using an 8-bit memory manipulation instruction. RESET input sets BRGC00 to 00H.
Symbol
7
6
5
4
3 0
2 0
1 0
0 0
Address FF73H
After reset 00H
R/W R/W
BRGC00 TPS003 TPS002 TPS001 TPS000
TPS003 TPS002 TPS001 TPS000 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fX/2 (2.5 MHz) fX/22 (1.25 MHz) fX/2 (625 kHz) fX/2 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/2 (39.1 kHz) fX/2 (19.5 kHz) Setting prohibited
8 7 4 3
3-bit counter source clock selection
n 1 2 3 4 5 6 7 8
Other than above
Cautions 1. When BRGC00 is written during a communication operation, the output of the baud rate generator is disrupted and communications cannot be performed normally. Be sure not to write to BRGC00 during a communication operation. 2. Do not select n = 1 during fX = 5.0 MHz operation because the baud rate rating is exceeded. Remarks 1. fX: Main system clock oscillation frequency 2. n: Value in the above table that is determined in the settings of TPS000 to TPS003 (1 n 8) 3. The parenthesized values apply to operation at fX = 5.0 MHz. If the internal clock is used as the serial clock for the 3-wire serial I/O mode, set the TPS000 to TPS003 bits to set the frequency of the serial clock. To obtain the frequency to be set, use the following formula. When the serial clock is input from off-chip, setting BRGC00 is unnecessary. Serial clock frequency = fX 2
n+1
[Hz]
fX: Main system clock oscillation frequency n: Value in the above table that is determined in the settings of TPS000 to TPS003 (1 n 8)
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(2)
Communication operation In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. transmitted/received bit by bit in synchronization with the serial clock. Transmit shift register 00 (TXS00/SIO00) and receive shift register 00 (RXS00) shift operations are performed in synchronization with the fall of the serial clock (SCK). Then transmit data is held in the SO latch and output from the SO pin. Also, receive data input to the SI pin is latched in receive buffer register 00 (RXB00/SIO00) on the rise of SCK. At the end of an 8-bit transfer, the operation of TXS00/SIO00 or RXS00 stops automatically, and the interrupt request signal (INTCSI00) is generated. Figure 13-11. 3-Wire Serial I/O Mode Timing Data is
SCK
1
2
3
4
5
6
7
8
SI
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
INTCSI00 Transfer start at the falling edge of SCK End of transfer
(3)
Transfer start Serial transfer is started by setting transfer data to transmit shift register 00 (TXS00/SIO00) when the following two conditions are satisfied. * Bit 7 (CSIE00) of serial operation mode register 00 (CSIM00) = 1 * Internal serial clock is stopped or SCK is a high level after 8-bit serial transfer. Caution If CSIE00 is set to 1 after data is written to TXS00/SIO00, transfer does not start.
Termination of 8-bit transfer stops the serial transfer automatically and generates the interrupt request signal (INTCSI00).
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14.1 Functions of LCD Controller/Driver
The functions of the LCD controller/driver of the PD789407A and 789417A Subseries are as follows. (1) (2) Automatic output of segment and common signals based on automatic display data memory read Five different display modes: * Static * 1/2 duty (1/2 bias) * 1/3 duty (1/2 bias) * 1/3 duty (1/3 bias) * 1/4 duty (1/3 bias) (3) (4) Four different frame frequencies, selectable in each display mode Up to 28 segment signal outputs (S0 to S27) and four common signal outputs (COM0 to COM3) Of these segment signal outputs, 12 outputs can be switched to I/O ports in 2-output units (P80/S27 to P87/S20 and P90/S19 to P93/S16). (5) (6) Voltage divider resistors (for LCD drive voltage generation) that a port itself can contain if so specified with a mask option Operation with a subsystem clock
Table 14-1 lists the maximum number of pixels that can be displayed in each display mode. Table 14-1. Maximum Number of Pixels
Bias Mode Number of Time Slices Common Signals Used COM0 (COM1 to COM3) COM0, COM1 COM0 to COM2 COM0 to COM2 COM0 to COM3 112 (28 segment signals, 4 common signals)Note 4 Maximum Number of Pixels
- 1/2
Static
28 (28 segment signals, 1 common signal)Note 1
2 3
56 (28 segment signals, 2 common signals)Note 2 84 (28 segment signals, 3 common signals)Note 3
1/3
3 4
Notes 1. Three-digit LCD panel, each digit having an 8-segment 2. Seven-digit LCD panel, each digit having a 4-segment 3. Nine-digit LCD panel, each digit having a 3-segment 4. Fourteen-digit LCD panel, each digit having a 2-segment
configuration. configuration. configuration. configuration.
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14.2 Configuration of LCD Controller/Driver
The LCD controller/driver consists of the following hardware. Table 14-2. Configuration of LCD Controller/Driver
Item Display outputs Configuration 28 segment signals (16 dedicated segment signals and 12 segment and I/O port signals) 4 common signals (COM0 to COM3) LCD display mode register 0 (LCDM0) LCD port selector 0 (LPS0) LCD clock control register 0 (LCDC0)
Control registers
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Selector
204
Figure 14-1. Block Diagram of LCD Controller/Driver
Internal bus LCD port selector 0 (LPS0) LCD clock control register 0 (LCDC0) LCDC03 LCDC02 LCDC01 LCDC00 2 2 LCD display mode register 0 (LCDM0) Display data memory FxxxH 76543210 FxxxH 76543210 P8x P9x FxxxH 7 6 5 4 3 2 1 0 Output latch Output latch LCDON0 VAON0 LIPS0 LCDM02 LCDM01 LCDM00 LPS05 LPS04 LPS03 LPS02 LPS01 LPS00 3 6 fX/23 fX/25 fX/27 fXT
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fLCD fLCD 26
Segment selector Prescaler fLCD 27 fLCD 28 fLCD 29 LCD clock selector LCDCL Timing controller LCDON 3210 Selector LCDON 3210 Selector LCDON 3210 Selector
LCD drive voltage controller
Common driver
P8x output buffer
Segment driver
P9x output buffer
Segment driver
Segment driver
VLC2 VLC1 VLC0 BIAS COM0 COM1 COM2 COM3
Sx/P8x
Sx/P9x
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14.3 Registers Controlling LCD Controller/Driver
The following three registers are used to control the LCD controller/driver. * LCD display mode register 0 (LCDM0) * LCD port selector 0 (LPS0) * LCD clock control register 0 (LCDC0) (1) LCD display mode register 0 (LCDM0) LCDM0 specifies whether to enable display operation. It also specifies the operation mode, LCD drive power supply, and display mode. LCDM0 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets LCDM0 to 00H. Figure 14-2. Format of LCD Display Mode Register 0
Symbol LCDM0 7 6 5 0 4 LIPS0 3 0 2 1 0 Address FFB0H After reset 00H R/W R/W
LCDON0 VAON0
LCDM02 LCDM01 LCDM00
LCDON0 0 1
Control of LCD display Display off (all segment outputs are deselected.) Display on
VAON0 0 1 Normal operation Low-voltage operation
LCD controller/driver operation modeNote
LIPS0 0 1 LCD drive power is not supplied.
LCD drive power supply selection
LCD drive power is supplied to the BIAS pin.
LCDM02 LCDM01 LCDM00
LCD controller/driver display mode selection Number of time slices Bias mode 1/3 1/3 1/2 1/2
0 0 0 0 1
0 0 1 1 0
0 1 0 1 0
4 3 2 3 Static Setting prohibited
Other than above
Note When the LCD display panel is not used, VAON0 and LIPS0 must be fixed to 0 to conserve power. Caution Before attempting to manipulate VAON0, set LIPS0 and LCDON0 to 0 to turn off the LCD.
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LCD port selector 0 (LPS0) LPS0 controls port and segment signal output switching. LPS0 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets LPS0 to 00H. Figure 14-3. Format of LCD Port Selector 0
Symbol LPS0
7 0
6 0
5
4
3
2
1
0
Address FFB1H
After reset 00H
R/W R/W
LPS05 LPS04 LPS03 LPS02 LPS01 LPS00
LPS05
LPS04
LPS03
LPS02
LPS01
LPS00
P93/S16, P92/S17 P91/S18, P90/S19 P87/S20, P86/S21 P85/S22, P84/S23 P83/S24, P82/S25 P81/S26, P80/S27 0 1 Used as ports (Pmn) Used as segments (Sx)
Cautions 1. Bits 6 and 7 must be fixed to 0. 2. Be sure to use segments in sequence from the smallest segment value (LPS05 LPS04 ... LPS00). Remark m = 8 n = 0 to 7 m = 9 n = 0 to 3 x = 16 to 27
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LCD clock control register 0 (LCDC0) LCDC0 specifies the LCD source clock and LCD clock. The frame frequency is determined according to the LCD clock and the number of time slices. LCDC0 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets LCDC0 to 00H. Figure 14-4. Format of LCD Clock Control Register 0
Symbol LCDC0
7 0
6 0
5 0
4 0
3
2
1
0
Address FFB2H
After reset 00H
R/W R/W
LCDC03 LCDC02 LCDC01 LCDC00
LCDC03 LCDC02 0 0 1 1 0 1 0 1 fX/27 (39.1 kHz) fXT (32.768 kHz) fX/25 (156.3 kHz) fX/23 (625 kHz)
Selection of LCD source clock frequency (fLCD)Note
LCDC01 LCDC00 0 0 1 1 0 1 0 1 fLCD/2
6
Selection of LCD clock (LCDCL) frequency
fLCD/27 fLCD/28 fLCD/29
Note Specify an LCD source clock (fLCD) frequency of at least 32 kHz. Remarks 1. fX: Main system clock oscillation frequency 2. fXT: Subsystem clock oscillation frequency 3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz. For example, Table 14-3 lists the frame frequencies used when fXT (32.768 kHz) is supplied to the LCD source clock (fLCD). Table 14-3. Frame Frequencies (Hz)
LCD Clock (LCDCL) Frequency Number of Time Slices Static 2 3 4 fXT/29 (64 Hz) 64 32 21 16 fXT/28 (128 Hz) 128 64 43 32 fXT/27 (256 Hz) 256 128 85 64 fXT/26 (512 Hz) 512 256 171 128
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14.4 Setting LCD Controller/Driver
Set the LCD controller/driver using the following procedure. <1> Set the initial values in the LCD display data memory (FA00H to FA1BH). <2> Set the pins to be used for segment output in LCD port selector 0 (LPS0). <3> Set the display and operation modes in LCD display mode register 0 (LCDM0). <4> Set the LCD clock in LCD clock control register 0 (LCDC0). Subsequent to this procedure, set the data to be displayed in the data memory.
14.5 LCD Display Data Memory
The LCD display data memory is mapped at addresses FA00H to FA1BH. Data in the LCD display data memory can be displayed on the LCD panel using the LCD controller/driver. Figure 14-5 shows the relationship between the contents of the LCD display data memory and the segment/common outputs. The part of the display data memory not used for display can be used as ordinary RAM. Figure 14-5. Relationship Between LCD Display Data Memory Contents and Segment/Common Outputs
Address FA00H FA01H FA02H FA03H b7 b6 b5 b4 b3 b2 b1 b0 S0 S1 S2 S3
FA09H FA1AH FA1BH
S25/P82 S26/P81 S27/P80
COM3
COM2
COM1
COM0
Caution
No memory is allocated to the higher 4 bits of the LCD display data memory. Be sure to fix there bits to 0.
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14.6 Common and Segment Signals
Each pixel of the LCD panel turns on when the potential difference between the corresponding common and segment signals becomes higher than a specific voltage (LCD drive voltage, VLCD). The pixels turn off when the potential difference becomes lower than VLCD. Applying DC voltage to the common and segment signals of an LCD panel causes deterioration. To avoid this problem, this LCD panel is driven by AC voltage. (1) Common signals Each common signal is selected sequentially according to a specified number of time slices at the timing listed in Table 14-4. In the static display mode, the same signal is output to COM0 to COM3. In the two-time-slice mode, leave the COM2 and COM3 pins open. In the three-time-slice mode, leave the COM3 pin open. Table 14-4. COM Signals
COM Signal Number of Time Slices Static display mode Two-time-slice mode Three-time-slice mode Four-time-slice mode Open Open Open COM0 COM1 COM2 COM3
(2)
Segment signals The segment signals correspond to 28 bytes of LCD display data memory (FA00H to FA1BH). Bits 0, 1, 2, and 3 of each byte are read in synchronization with COM0, COM1, COM2, and COM3, respectively. If a bit is 1, it is converted to the select voltage, and if it is 0, it is converted to the deselect voltage. The conversion results are output to the segment pins (S0 to S27). Note that S16 to S27 can also be used as I/O port pins. Check, with the information given above, what combination of front-surface electrodes (corresponding to the segment signals) and rear-surface electrodes (corresponding to the common signals) forms display patterns in the LCD display data memory, and write the bit data that corresponds to the desired display pattern on a one-to-one basis. LCD display data memory bits 1 and 2, bits 2 and 3, and bit 3 are not used for LCD display in the static display, two-time slot, and three-time slot modes, respectively. So these bits can be used for purposes other than display. LCD display data memory bits 4 to 7 are fixed to 0.
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(3)
Output waveforms of common and segment signals The voltages listed in Table 14-5 are output as common and segment signals. When both common and segment signals are at the select voltage, a display on-voltage of VLCD is obtained. The other combinations of the signals correspond to the display off-voltage. Table 14-5. LCD Drive Voltage (a) Static display mode
Segment Signal Select Signal Level VSS0/VLC0 -VLCD/+VLCD 0 V/0 V Deselect Signal Level VLC0/VSS0
Common Signal VLC0/VSS0
(b) 1/2 bias method
Segment Signal Common Signal Select signal level Deselect signal level VLC0/VSS0 VLC1 = VLC2 -VLCD/+VLCD 1 1 - VLCD/+ VLCD 2 2 Select Signal Level VSS0/VLC0 0 V/0 V + 1 1 VLCD/- VLCD 2 2 Deselect Signal Level VLC0/VSS0
(c) 1/3 bias method
Segment Signal Common Signal Select signal level Deselect signal level VLC0/VSS0 VLC2/VLC1 -VLCD/+VLCD - 1 1 VLCD/+ VLCD 3 3 Select Signal Level VSS0/VLC0 - Deselect Signal Level VLC1/VLC2 1 1 VLCD/+ VLCD 3 3 1 1 - VLCD/+ VLCD 3 3
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Figure 14-6 shows the common signal waveforms, and Figure 14-7 shows the voltages and phases of the common and segment signals. Figure 14-6. Common Signal Waveforms (a) Static display mode
VLC0 COMn (Static display) VSS0 TF = T VLCD
T: One LCD clock period
TF: Frame frequency (b) 1/2 bias method
VLC0
COMn VLC2 (Two-time slot mode) VSS0 TF = 2 x T VLC0 COMn VLC2 (Three-time slot mode) VSS0 TF = 3 x T VLCD VLCD
T: One LCD clock period
TF: Frame frequency (c) 1/3 bias method
VLC0
COMn (Three-time slot mode) TF = 3 x T
VLC1 VLC2 VSS0
VLCD
VLC0 COMn (Four-time slot mode) TF = 4 x T VLC1 VLC2 VSS0 VLCD
T: One LCD clock period
TF: Frame frequency
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Figure 14-7. Voltages and Phases of Common and Segment Signals (a) Static display mode
Select Deselect VLC0 Common signal VSS0 VLC0 Segment signal VSS0 T T VLCD VLCD
T: One LCD clock period (b) 1/2 bias method
Select Deselect VLC0 Common signal VLC2 VSS0 VLC0 Segment signal VLC2 VSS0 T T VLCD VLCD
T: One LCD clock period (c) 1/3 bias method
Select Deselect VLC0 Common signal VLC1 VLC2 VSS0 VLC0 VLC1 VLC2 VSS0 T T VLCD
Segment signal
VLCD
T: One LCD clock period
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14.7 Supplying LCD Drive Voltages VLC0, VLC1, and VLC2
The mask ROM versions (except the PD78F9418A) of the LCD display can incorporate voltage divider resistors for generating LCD drive power as specified using a mask option. resistors. The LCD drive voltage can be supplied to the BIAS pin to support various LCD drive voltage levels. Table 14-6. LCD Drive Voltages (with On-Chip Voltage Divider Resistors)
Bias Method LCD Drive Voltage Pin VLC0 VLC1 VLC2 VLCD 2 VLCD 3 1 VLCD 3 VLCD 1 VLCDNote 2 VLCD 2 VLCD 3 1 VLCD 3 No Bias (Static) 1/2 Bias Method 1/3 Bias Method
Incorporating voltage divider resistors can
generate LCD drive voltages that meet each bias method listed in Table 14-6, without using external voltage divider
Note For the 1/2 bias method, it is necessary to connect the VLC1 and VLC2 pins externally. Remarks 1. If the BIAS and VLC0 pins are open, VLCD = 3 5 2. If the BIAS and VLC0 pins are connected, VLCD = VDD. Figure 14-8 shows examples of generating LCD drive voltages internally according to Table 14-6. VDD (if voltage divider resistors are included).
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Figure 14-8. Examples of LCD Drive Power Connections (with On-Chip Voltage Divider Resistors) (a) 1/3 bias method and static display mode (VDD = 5 V and VLCD = 3 V)
VDD
(b) 1/2 bias method (VDD = 5 V and VLCD = 5 V)
VDD
LIPS0
P-ch BIAS pin 2R VLC0 R VLC1
LIPS0
P-ch BIAS pin 2R VLC0 R VLC1
VLCD VLC2
R
VLCD VLC2
R
R VSS0 VSS VLCD = 3/5 VDD VSS0
R
VSS VLCD = VDD
(c) 1/3 bias method and static display mode (VDD = 5 V and VLCD = 5 V)
VDD
LIPS0
P-ch BIAS pin 2R VLC0 R VLC1
VLCD VLC2
R
R VSS0 VSS VLCD = VDD
LIPS0: Bit 4 of LCD display mode register 0 (LCDM0)
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14.8 Display Modes
14.8.1 Static display example Figure 14-10 shows how the three-digit LCD panel having the display pattern shown in Figure 14-9 is connected to the segment signals (S0 to S23) and the common signal (COM0) of the PD789407A or 789417A Subseries chip. This example displays data "12.3" in the LCD panel. The contents of the display data memory (addresses FA00H to FA17H) correspond to this display. The following description focuses on numeral "2." ( ) displayed in the second digit. To display "2." in the LCD panel, it is necessary to apply the select or deselect voltage to the S8 to S15 pins according to Table 14-7 at the timing of the common signal COM0; see Figure 14-9 for the relationship between the segment signals and LCD segments. Table 14-7. Select and Deselect Voltages (COM0)
Segment Common COM0 Select Deselect Select Select Deselect Select Select Select S8 S9 S10 S11 S12 S13 S14 S15
According to Table 14-7, it is determined that the bit-0 pattern of the display data memory locations (FA08H to FA0FH) must be 10110111. Figure 14-11 shows the LCD drive waveforms of S11 and S12, and COM0. When the select voltage is applied to S11 at the timing of COM0, an alternate rectangle waveform, +VLCD/-VLCD, is generated to turn on the corresponding LCD segment. COM1 to COM3 are supplied with the same waveform as for COM0. So, COM0 to COM3 may be connected together to increase the driving capacity. Figure 14-9. Static LCD Display Pattern and Electrode Connections
S8n+3
S8n+4
S8n+2 S8n+5 COM0
S8n+6
S8n+1 S8n
S8n+7
Remark
n = 0 to 2
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Figure 14-10. Example of Connecting Static LCD Panel
Timing strobe
COM 3 COM 2 COM 1 COM 0 Bit 0 Bit 1 Bit 2 Bit 3
Can be connected together
000001101110110110101110
FA00H 1 2 3 4 5 6 7 8 9 Data memory address A B C D E F FA10H 1 2 3 4 5 6 7
xxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxx
S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S 11 S 12 S 13 S 14 S 15 S 16 S 17 S 18 S 19 S 20 S 21 S 22 S 23 LCD panel S 10
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Figure 14-11. Static LCD Drive Waveform Examples
TF
VLC0 COM0 VSS0
VLC0 S11 VSS0
VLC0 S12 VSS0
+VLCD
COM0 to S11
0
-VLCD
+VLCD
COM0 to S12
0
-VLCD
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14.8.2 Two-time-slice display example Figure 14-13 shows how the seven-digit LCD panel having the display pattern shown in Figure 14-12 is connected to the segment signals (S0 to S27) and the common signals (COM0 and COM1) of the PD789407A or 789417A Subseries chip. This example displays data "123456.7" in the LCD panel. The contents of the display data memory (addresses FA00H to FA1BH) correspond to this display. The following description focuses on numeral "3" ( ) displayed in the fifth digit. To display "3" in the LCD panel, it is necessary to apply the select or deselect voltage to the S16 to S19 pins according to Table 14-8 at the timing of the common signals COM0 and COM1; see Figure 14-12 for the relationship between the segment signals and LCD segments. Table 14-8. Select and Deselect Voltages (COM0 and COM1)
Segment Common COM0 COM1 Select Deselect Select Select Deselect Select Deselect Select S16 S17 S18 S19
According to Table 14-8, it is determined that the display data memory location (FA13H) that corresponds to S19 must contain xx10. Figure 14-14 shows examples of LCD drive waveforms between the S19 signal and each common signal. When the select voltage is applied to S19 at the timing of COM1, an alternate rectangle waveform, +VLCD/-VLCD, is generated to turn on the corresponding LCD segment. Figure 14-12. Two-Time-Slice LCD Display Pattern and Electrode Connections
;;;;; ;;;
S4n+2
S4n+1
COM0
S4n+3
; ;;;; ;;;;; ;
S4n
COM1
Remark
n = 0 to 6
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Figure 14-13. Example of Connecting Two-Time-Slice LCD Panel
Timing strobe
COM 3 COM 2 COM 1 COM 0
Open Open
Bit 0
Bit 1
Bit 2
Bit 3
0011101000110111010111010111
0000111011100010111011110100 xxxxxxxxxxxxxxxxxxxxxxxxxxxx
FA00H 1 2 3 4 5 6 7 8 9
xxxxxxxxxxxxxxxxxxxxxxxxxxxx
S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S 11 S 12 S 13 S 14 S 15 S 16 S 17 S 18 S 19 S 20 S 21 S 22 S 23 S 24 S 25 S 26 S 27 S 10
Data memory address
A B C D E F FA10H 1 2 3 4 5 6 7 8 9 A B
x: Can always be used to store any data because the two-time-slice mode is being used.
LCD panel
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Figure 14-14. Two-Time-Slice LCD Drive Waveform Examples (1/2 Bias Method)
TF
VLC0 COM0 VLC1,2 VSS0
VLC0 COM1 VLC1,2 VSS0
VLC0 S19 VLC1,2 VSS0
+VLCD +1/2VLCD COM0 to S19 0 -1/2VLCD -VLCD
+VLCD +1/2VLCD COM1 to S19 0 -1/2VLCD -VLCD
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14.8.3 Three-time-slice display example Figure 14-16 shows how the nine-digit LCD panel having the display pattern shown in Figure 14-15 is connected to the segment signals (S0 to S26) and the common signals (COM0 to COM2) of the PD789407A or 789417A Subseries chip. This example displays data "123456.789" in the LCD panel. The contents of the display data memory (addresses FA00H to FA1AH) correspond to this display. The following description focuses on numeral "6." ( ) displayed in the fourth digit. To display "6." in the LCD panel, it is necessary to apply the select or deselect voltage to the S9 to S11 pins according to Table 14-9 at the timing of the common signals COM0 to COM2; see Figure 14-15 for the relationship between the segment signals and LCD segments. Table 14-9. Select and Deselect Voltages (COM0 to COM2)
Segment Common COM0 COM1 COM2 Deselect Select Select Select Select Select Select Select - S9 S10 S11
According to Table 14-9, it is determined that the display data memory location (FA09H) that corresponds to S9 must contain x110. Figures 14-17 and 14-18 show examples of LCD drive waveforms between the S9 signal and each common signal in the 1/2 and 1/3 bias methods, respectively. When the select voltage is applied to S9 at the timing of COM1 or COM2, an alternate rectangle waveform, +VLCD/-VLCD, is generated to turn on the corresponding LCD segment. Figure 14-15. Three-Time-Slice LCD Display Pattern and Electrode Connections
S3n+1 COM0
S3n+2
Remark
n = 0 to 8
;; ;; ;; ; ;; ;
S3n
;; ;;; ;; ;; ;;; ;; ;; ;; ;;
COM2
COM1
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Figure 14-16. Example of Connecting Three-Time-Slice LCD Panel
Timing strobe
COM 3 COM 2 COM 1 COM 0
Bit 0 Bit 1 Bit 2 Bit 3
Open
FA00H 1 2 3 4 5 6 7 8 9
Data memory address
001110011011011111001111011 x' 0 0 x' 1 0 x' 1 0 x' 0 0 x' 1 0 x' 1 1 x' 0 0 x' 1 0 x' 0 0 xxxxxxxxxxxxxxxxxxxxxxxxxxx
001011011101110110111111111
S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S 11 S 12 S 13 S 14 S 15 S 16 S 17 S 18 S 19 S 20 S 21 S 22 S 23 S 24 S 25 S 26
LCD panel
A B C D E F FA10H 1 2 3 4 5 6 7 8 9 A
S 10
x': Can be used to store any data because there is no corresponding segment in the LCD panel. x: Can always be used to store any data because the three-time-slice mode is being used.
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Figure 14-17. Three-Time-Slice LCD Drive Waveform Examples (1/2 Bias Method)
TF
VLC0 COM0 VLC1,2 VSS0
VLC0 COM1 VLC1,2 VSS0
VLC0 COM2 VLC1,2 VSS0
VLC0 S9 VLC1,2 VSS0
+VLCD +1/2VLCD COM0 to S9 0 -1/2VLCD -VLCD
+VLCD +1/2VLCD COM1 to S9 0 -1/2VLCD -VLCD
+VLCD +1/2VLCD COM2 to S9 0 -1/2VLCD -VLCD
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Figure 14-18. Three-Time-Slice LCD Drive Waveform Examples (1/3 Bias Method)
TF
VLC0 COM0 VLC1 VLC2 VSS0 VLC0 COM1 VLC1 VLC2 VSS0 VLC0 COM2 VLC1 VLC2 VSS0 VLC0 S9 VLC1 VLC2 VSS0 +VLCD
+1/3VLCD COM0 to S9 0 -1/3VLCD
-VLCD +VLCD
+1/3VLCD COM1 to S9 0 -1/3VLCD
-VLCD +VLCD
+1/3VLCD COM2 to S9 0 -1/3VLCD
-VLCD
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14.8.4 Four-time-slice display example Figure 14-20 shows how the 14-digit LCD panel having the display pattern shown in Figure 14-19 is connected to the segment signals (S0 to S27) and the common signals (COM0 to COM3) of the PD789407A or 789417A Subseries chip. This example displays data "123456.78901234" in the LCD panel. The contents of the display data memory (addresses FA00H to FA1BH) correspond to this display. The following description focuses on numeral "6." ( ) displayed in the ninth digit. To display "6." in the LCD panel, it is necessary to apply the select or deselect voltage to the S16 and S17 pins according to Table 14-10 at the timing of the common signals COM0 to COM3; see Figure 14-19 for the relationship between the segment signals and LCD segments. Table 14-10. Select and Deselect Voltages (COM0 to COM3)
Segment Common COM0 COM1 COM2 COM3 Select Deselect Select Select Select Select Select Select S16 S17
According to Table 14-10, it is determined that the display data memory location (FA16H) that corresponds to S16 must contain 1101. Figure 14-21 shows examples of LCD drive waveforms between the S16 signal and each common signal. When the select voltage is applied to S16 at the timing of COM0, an alternate rectangle waveform, +VLCD/-VLCD, is generated to turn on the corresponding LCD segment. Figure 14-19. Four-Time-Slice LCD Display Pattern and Electrode Connections
S2n
Remark
;;;; ; ;;;;;; ;; ;
S2n+1
COM0
COM1
COM2 COM3
n = 0 to 13
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Figure 14-20. Example of Connecting Four-Time-Slice LCD Panel
Timing strobe
COM 3 COM 2 COM 1 COM 0
Bit 0
Bit 1
Bit 2
Bit 3
0001011011111111111100010110
0111111110100111110101111111
0110010101110111011101100101
FA00H 1 2 3 4 5 6 7 8 9
0010100010110010001000101000
S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S 11 S 12 S 13 S 14 S 15 S 16 S 17 S 18 S 19 S 20 S 21 S 22 S 23 S 24 S 25 S 26 S 27 S 10
Data memory address
A B C D E F FA10H 1 2 3 4 5 6 7 8 9 A B
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Figure 14-21. Four-Time-Slice LCD Drive Waveform Examples (1/3 Bias Method)
TF
COM0
; ;
; ;
VLC0 VLC1 VLC2 VSS0 VLC0
COM1
VLC1 VLC2 VSS0 VLC0
COM2
VLC1 VLC2 VSS0 VLC0
COM3
VLC1 VLC2 VSS0 VLC0
S16
VLC1 VLC2 VSS0 +VLCD
+1/3VLCD COM0 to S16 0 -1/3VLCD
-VLCD +VLCD
+1/3VLCD COM1 to S16 0 -1/3VLCD
-VLCD
Remark
The waveforms for COM2 to S16 and COM3 to S16 are omitted.
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CHAPTER 15 INTERRUPT FUNCTIONS
15.1 Interrupt Function Types
The following two types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally. It does not undergo interrupt priority control and is given top priority over all other interrupt requests. A standby release signal is generated. One interrupt source from the watchdog timer is incorporated as a non-maskable interrupt. (2) Maskable interrupt These interrupts undergo mask control. If two or more interrupts with the same priority are simultaneously generated, each interrupt has a predetermined priority as shown in Table 15-1. A standby release signal is generated. Five external interrupt and 11 internal interrupt sources are incorporated as maskable interrupts.
15.2 Interrupt Sources and Configuration
A total of 17 non-maskable and maskable interrupts are incorporated as interrupt sources (see Table 15-1).
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Table 15-1. Interrupt Source List
Interrupt Type PriorityNote 1 Name Non-maskable - 0 INTWDT Interrupt Source Trigger Watchdog timer overflow (with watchdog timer mode 1 selected) Watchdog timer overflow (with interval timer mode selected) Pin input edge detection External 0006H 0008H 000AH 000CH End of serial interface 00 UART reception End of serial interface 00 3-wire SIO transfer reception End of serial interface 00 UART transmission Watch timer interrupt Interval timer interrupt Generation of matching signal of 8-bit timer/event counter 00 Generation of matching signal of 8-bit timer/event counter 01 Generation of matching signal of 8-bit timer 02 Generation of matching signal of 16-bit timer 50 Key return signal detection A/D conversion completion signal Comparator signal External Internal 0010H Internal 000EH (B) Internal Internal/ External Vector Table Address 0004H Basic Configuration TypeNote 2 (A)
Maskable
INTWDT
(B)
1 2 3 4 5
INTP0 INTP1 INTP2 INTP3 INTSR00
(C)
INTCSI00
6
INTST00
7 8 9
INTWT INTWTI INTTM00
0012H 0014H 0016H
10
INTTM01
0018H
11
INTTM02
001AH
12
INTTM50
001CH
13 14 15
INTKR00 INTAD0 INTCMP0
001EH 0020H 0022H
(C) (B)
Notes 1. "Priority" is the priority order when several maskable interrupts are generated at the same time. 0 is the highest and 15 is the lowest. 2. Basic configuration types (A) to (C) correspond to (A) to (C) in Figure 15-1.
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Figure 15-1. Basic Configuration of Interrupt Function (A) Internal non-maskable interrupt
Internal bus
Interrupt request
Vector table address generator
Standby release signal
(B) Internal maskable interrupt
Internal bus
MK
IE
Interrupt request
IF
Vector table address generator
Standby release signal
(C) External maskable interrupt
Internal bus
External interrupt mode register (INTM0, INTM1)
MK
IE
Interrupt request
Edge detector
IF
Vector table address generator
Standby release signal
IF: IE:
Interrupt request flag Interrupt enable flag
MK: Interrupt mask flag
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15.3 Registers Controlling Interrupt Function
The following five registers are used to control the interrupt functions. * Interrupt request flag registers 0, 1 (IF0 and IF1) * Interrupt mask flag registers 0, 1 (MK0 and MK1) * External interrupt mode registers 0, 1 (INTM0 and INTM1) * Program status word (PSW) * Key return mode register 00 (KRM00) Table 15-2 lists the interrupt request flag and interrupt mask flag names corresponding to interrupt requests. Table 15-2. Flags Corresponding to Interrupt Request Signal Name
Interrupt Request Signal Name INTWDT INTP0 INTP1 INTP2 INTP3 INTSR00/INTCSI00 INTST00 INTWT INTWTI INTTM00 INTTM01 INTTM02 INTTM50 INTKR00 INTAD0 INTCMP0 TMIF4 PIF0 PIF1 PIF2 PIF3 SRIF00 STIF00 WTIF WTIIF TMIF00 TMIF01 TMIF02 TMIF50 KRIF00 ADIF0 CMPIF0 Interrupt Request Flag TMMK4 PMK0 PMK1 PMK2 PMK3 SRMK00 STMK00 WTMK WTIMK TMMK00 TMMK01 TMMK02 TMMK50 KRMK00 ADMK0 CMPMK0 Interrupt Mask Flag
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(1)
Interrupt request flag registers 0, 1 (IF0 and IF1) The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is executed. It is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon RESET input. IF0 and IF1 are set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets IF0 and IF1 to 00H. Figure 15-2. Format of Interrupt Request Flag Register
Symbol <7> IF0
<6>
<5>
<4>
<3> PIF2 <3>
<2> PIF1 <2>
<1>
<0>
Address FFE0H
After reset 00H
R/W R/W
WTIF STIF00 SRIF00 PIF3 <7> <6> <5> <4>
PIF0 TMIF4 <1> <0>
IF1
CMPIF0 ADIF0 KRIF00 TMIF50 TMIF02 TMIF01 TMIF00 WTIIF
FFE1H
00H
R/W
XXIFX 0 1
Interrupt request flag No interrupt request signal is generated Interrupt request signal is generated; Interrupt request state
Cautions 1. The TMIF4 flag is R/W enabled only when the watchdog timer is used as an interval timer. If watchdog timer mode 1 or 2 is used, set the TMIF4 flag to 0. 2. Because port 2 has an alternate function as an external interrupt input, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. Therefore, the interrupt mask flag should be set to 1 before using the output mode. 3. If an interrupt is acknowledged, the interrupt request flag is automatically cleared before the interrupt routine is entered.
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(2)
Interrupt mask flag registers 0, 1 (MK0 and MK1) The interrupt mask flag is used to enable/disable the corresponding maskable interrupt service. MK0 and MK1 are set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets MK0 and MK1 to FFH. Figure 15-3. Format of Interrupt Mask Flag Register
Symbol MK0
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
Address FFE4H
After reset FFH
R/W R/W
WTMK STMK00 SRMK00 PMK3 PMK2 PMK1 PMK0 TMMK4 <7> <6> <5> <4> <3> <2> <1> <0>
MK1
CMPMK0 ADMK0 KRMK00 TMMK50 TMMK02 TMMK01 TMMK00 WTIMK
FFE5H
FFH
R/W
XXMKX 0 1 Interrupt servicing enabled Interrupt servicing disabled
Interrupt servicing control
Cautions 1. If the TMMK4 flag is read when the watchdog timer is used in watchdog timer mode 1 or 2, its value becomes undefined. 2. Because port 2 has an alternate function as an external interrupt input, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. Therefore, the interrupt mask flag should be set to 1 before using the output mode.
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(3)
External interrupt mode register 0 (INTM0) This register is used to specify a valid edge for INTP0 to INTP2. INTM0 is set using an 8-bit memory manipulation instruction. RESET input sets INTM0 to 00H. Figure 15-4. Format of External Interrupt Mode Register 0
Symbol INTM0
7
6
5
4
3
2
1 0
0 0
Address FFECH
After reset 00H
R/W R/W
ES21 ES20 ES11 ES10 ES01 ES00
ES21 ES20 0 0 1 1 0 1 0 1 Falling edge Rising edge Setting prohibited Both rising and falling edges
INTP2 valid edge selection
ES11 ES10 0 0 1 1 0 1 0 1 Falling edge Rising edge Setting prohibited Both rising and falling edges
INTP1 valid edge selection
ES01 ES00 0 0 1 1 0 1 0 1 Falling edge Rising edge Setting prohibited Both rising and falling edges
INTP0 valid edge selection
Cautions 1. Bits 0 and 1 must be fixed to 0. 2. Before setting the INTM0 register, be sure to set xxMKx of the relevant interrupt mask flag to 1 to disable interrupts. After that, clear the interrupt mask flag (xxMKx = 0) to enable interrupts after clearing the interrupt request flag (xxIFx = 0).
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(4)
External interrupt mode register 1 (INTM1) INTM1 is used to specify a valid edge for INTP3 and INTCMP0. INTM1 is set using an 8-bit memory manipulation instruction. RESET input sets INTM1 to 00H. Figure 15-5. Format of External Interrupt Mode Register 1
Symbol INTM1
7
6
5 0
4 0
3 0
2 0
1
0
Address FFEDH
After reset 00H
R/W R/W
ES61 ES60
ES31 ES30
ES61 ES60 0 0 1 1 0 1 0 1 Falling edge Rising edge Setting prohibited Both rising and falling edges
INTCMP0 valid edge selection
ES31 ES30 0 0 1 1 0 1 0 1 Falling edge Rising edge Setting prohibited Both rising and falling edges
INTP3 valid edge selection
Cautions 1. Bits 2 to 5 must be fixed to 0. 2. Before setting INTM1, set the corresponding interrupt mask flag register to 1 to disable interrupts. After that, clear (0) the corresponding interrupt request flag to enable interrupts, then clear the corresponding interrupt mask flag register.
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(5)
Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for interrupt requests. The IE flag to set maskable interrupt enable/disable is mapped to the PSW. Besides 8-bit unit read/write, this register can carry out operations via bit manipulation instructions and dedicated instructions (EI, DI). When a vectored interrupt is acknowledged, the PSW is automatically saved into a stack, and the IE flag is reset to 0. RESET input sets the PSW to 02H. Figure 15-6. Configuration of Program Status Word
Symbol PSW
7 IE
6 Z
5 0
4 AC
3 0
2 0
1 1
0 CY
After reset 02H
Used when normal instruction is executed IE 0 1 Disabled Enabled Interrupt acknowledge enable/disable
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(6)
Key return mode register 00 (KRM00) This register sets the pin that detects a key return signal (falling edge of port 4). KRM00 is set using a 1-bit or 8-bit memory manipulation instruction. Bit 0 (KRM000) is set in 4-bit units for KR0/P40 to KR3/P43 pins. Bits 4 and 5 (KRM004 and KRM005) are set in 1-bit units for KR4/P44 and KR5/P45 pins, respectively. RESET input sets KRM00 to 00H. Figures 15-7 and 15-8 show the format of key return mode register 00 and the block diagram of the falling edge detector, respectively. Figure 15-7. Format of Key Return Mode Register 00
Symbol KRM00
7 0
6 0
5
4
3 0
2 0
1 0
0 KRM000
Address FFF5H
After reset 00H
R/W R/W
KRM005 KRM004
KRM00n 0 1 No detection
Key return signal detection selection
Detection (detecting falling edge of port 4)
Cautions 1. Bits 1 to 3, 6, and 7 must be fixed to 0. 2. When the KRM00 register is set to 1, a pull-up resistor is connected automatically. However, the pull-up resistor is cut if the pin is in output mode. 3. Before setting KRM00, always set bit 5 of MK1 (KRMK00 = 1) to disable interrupts in advance. After setting KRM00, clear bit 5 of MK1 (KRMK00 = 0) after clearing bit 5 of IF1 (KRIF00 = 0) to enable interrupts. 4. The key return signal cannot be detected while even one of the pins that specify detection of the key return signal is low, even if a falling edge is generated at other key return pins. Remark n = 0, 4, 5 Figure 15-8. Block Diagram of Falling Edge Detector
Key return mode register 00 (KRM00)
Note
P40/KR0 P41/KR1 Selector P42/KR2 P43/KR3 P44/KR4 P45/KR5 KRMK Falling edge detector KRIF00 set signal
Standby release signal
Note Selector that selects the pin used for falling edge input
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15.4 Operation of Interrupt Servicing
15.4.1 Non-maskable interrupt acknowledgment operation The non-maskable interrupt is unconditionally acknowledged even when interrupts are disabled. It is not subject to interrupt priority control and takes precedence over all other interrupts. When the non-maskable interrupt request is acknowledged, the PSW and PC are saved to the stack in that order, the IE flag is reset to 0, the contents of the vector table are loaded to the PC, and then program execution branches. Caution During non-maskable interrupt servicing program execution, do not input another nonmaskable interrupt request; if it is input, the servicing program will be interrupted and the new non-maskable interrupt request will be acknowledged.
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Figure 15-9. Flowchart of Non-Maskable Interrupt Request Acknowledgment
Start
WDTM4 = 1 (watchdog timer mode is selected) Yes
No Interval timer
WDT overflows Yes
WDTM3 = 0
No
(non-maskable interrupt is selected) Yes Interrupt request is generated
No Reset processing
Interrupt servicing is started
WDTM: Watchdog timer mode register WDT: Watchdog timer
Figure 15-10. Timing of Non-Maskable Interrupt Request Acknowledgment
CPU processing Instruction Instruction
Saving PSW and PC, and jump to interrupt servicing
Interrupt servicing program
TMIF4
Figure 15-11. Non-Maskable Interrupt Request Acknowledgment
Main routine
First interrupt servicing
NMI request (first)
NMI request (second)
Second interrupt servicing
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15.4.2 Maskable interrupt acknowledgment operation A maskable interrupt can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. A vectored interrupt is acknowledged in the interrupt enabled status (when the IE flag is set to 1). The time required to start the interrupt servicing after a maskable interrupt request has been generated is as follows: Table 15-3. Time from Generation of Maskable Interrupt Request to Servicing
Minimum Time 9 clocks Maximum TimeNote 19 clocks
Note The wait time is maximum when an interrupt request is generated immediately before the BT or BF instruction. Remark 1 clock: 1 fCPU (fCPU: CPU clock)
When two or more maskable interrupt requests are generated at the same time, they are acknowledged starting from the one assigned the highest priority by the priority specification flag. An interrupt held pending is acknowledged when the status in which it can be acknowledged is set. Figure 15-12 shows the algorithm of acknowledging interrupts. When a maskable interrupt request is acknowledged, the PSW and PC are saved to the stack in that order, the IE flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded to the PC, and execution branches. To restore from interrupt servicing, use the RETI instruction. Figure 15-12. Interrupt Acknowledgment Program Algorithm
Start
No xxIF = 1 ? Yes (interrupt request generated) No xxMK = 0 ? Yes No IE = 1 ?
Interrupt request pending
Yes Vectored interrupt servicing
Interrupt request pending
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Figure 15-13. Interrupt Request Acknowledgment Timing (Example: MOV A, r)
8 clocks Clock
CPU
MOV A, r
Saving PSW and PC, and jump to interrupt servicing
Interrupt servicing program
Interrupt request
If the interrupt request has generated an interrupt request flag (XXIF) by the time the instruction clocks under execution, n clocks (n = 4 to 10), are n - 1, interrupt request acknowledgment processing will start following the completion of the instruction under execution. Figure 15-13 shows an example using the 8-bit data transfer instruction MOV A, r. Because this instruction is executed in 4 clocks, if an interrupt request is generated between the start of execution and the 3rd clock, interrupt request acknowledgment processing will take place following the completion of MOV A, r. Figure 15-14. Interrupt Request Acknowledgment Timing (When Interrupt Request Flag Is Generated in Final Clock Under Execution)
8 clocks Clock
CPU
NOP
MOV A, r
Saving PSW and PC, and jump to interrupt servicing
Interrupt servicing program
Interrupt request
If the interrupt request flag (XXIF) is generated in the final clock of the instruction, interrupt request acknowledgment processing will begin after execution of the next instruction is complete. Figure 15-14 shows an example whereby an interrupt request was generated in the 2nd clock of NOP (a 2-clock instruction). In this case, the interrupt request will be processed after execution of MOV A, r, which follows NOP, is complete. Caution When interrupt request flag registers 0 and 1 (IF0 and IF1) or interrupt mask flag registers 0 and 1 (MK0 and MK1) are being accessed, interrupt requests will be held pending. 15.4.3 Multiple interrupt servicing Processing in which another interrupt request is acknowledged while an interrupt request is serviced is called multiple interrupt servicing. Multiple interrupts are not performed unless an interrupt request is enabled (IE = 1) (except non-maskable interrupt request). The other interrupt request is disabled (IE = 0) at the time when an interrupt request is acknowledged. Therefore, it is necessary to set (1) the IE flag to realize the interrupt enable state using an EI instruction during interrupt request servicing in order to enable multiple interrupt servicing.
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Figure 15-15. Example of Multiple Interrupt Example 1. Acknowledging multiple interrupts
Main processing INTxx processing INTyy processing
EI
IE = 0
EI
IE = 0
INTxx
INTyy
RETI
RETI
The interrupt request INTyy is acknowledged and multiple interrupts are performed during the interrupt INTxx processing. Before each interrupt request is acknowledged, the EI instruction is issued and the interrupt request is enabled.
Example 2. Multiple interrupts are not performed because interrupts are disabled
Main processing INTxx processing INTyy processing
EI
IE = 0
INTyy RETI
INTyy is held pending
INTxx
IE = 0
RETI
Interrupt requests are disabled (the EI instruction is not issued) in the interrupt INTxx processing. The interrupt request INTyy is not acknowledged and multiple interrupts are not performed. acknowledged after INTxx servicing is completed. IE = 0: Interrupt request disabled INTyy is held pending and is
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15.4.4 Putting interrupt requests on hold If an interrupt (such as a maskable, non-maskable, or external interrupt) is requested when a certain type of instruction is being executed, the interrupt request will not be acknowledged until the instruction is completed. Such instructions include: * Instructions that manipulate interrupt request flag registers 0, 1 (IF0 and IF1) * Instructions that manipulate interrupt mask flag registers 0, 1 (MK0 and MK1)
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CHAPTER 16 STANDBY FUNCTION
16.1 Standby Function and Configuration
16.1.1 Standby function The standby function is used to reduce the power consumption of the system and can be effected in the following two modes: (1) HALT mode This mode is set when the HALT instruction is executed. The HALT mode stops the operation clock of the CPU. The system clock oscillator continues oscillating. This mode does not reduce the power consumption as much as the STOP mode, but is useful for resuming processing immediately when an interrupt request is generated, or for intermittent operations. (2) STOP mode This mode is set when the STOP instruction is executed. The STOP mode stops the main system clock oscillator and stops the entire system. The power consumption of the CPU can be substantially reduced in this mode. The data memory can be retained at the low voltage (VDD = 1.8 V). Therefore, this mode is useful for retaining the contents of the data memory at an extremely low current. The STOP mode can be released by an interrupt request, so that this mode can be used for intermittent operation. However, some time is required until the system clock oscillator stabilizes after the STOP mode has been released. If processing must be resumed immediately by using an interrupt request, therefore, use the HALT mode. In both modes, the previous contents of the registers, flags, and data memory before setting the standby mode are all retained. In addition, the statuses of the output latch of the I/O ports and output buffer are also retained. Caution To set the STOP mode, be sure to stop the operations of the peripheral hardware, and then execute the STOP instruction.
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16.1.2 Standby function control register The wait time after the STOP mode is released upon interrupt request until oscillation stabilizes is controlled by the oscillation stabilization time selection register (OSTS). OSTS is set using an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H. However, it takes 2 /fX, not 2 /fX, until the STOP mode is released by RESET input. Figure 16-1. Format of Oscillation Stabilization Time Selection Register
Symbol OSTS 7 0 6 0 5 0 4 0 3 0 2 1 0 Address FFFAH After reset 04H R/W R/W
15 17
OSTS2 OSTS1 OSTS0
OSTS2 OSTS1 OSTS0 0 0 1 0 1 0 0 0 0 212/fX (819 215/fX (6.55
Oscillation stabilization time selection
s)
ms)
217/fX (26.2 ms) Setting prohibited
Other than above
Caution
The wait time after the STOP mode is released does not include the time from STOP mode release to clock oscillation start ("a" in the figure below), regardless of release by RESET input or by interrupt generation.
STOP mode release X1 pin voltage waveform VSS0, VSS1 a
Remarks 1. fX: Main system clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz.
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16.2 Operation of Standby Function
16.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. The operation status in the HALT mode is shown in the following table. Table 16-1. HALT Mode Operating Status
Item HALT Mode Operation Status While Main System Clock Is Running While the subsystem clock is running Main system clock generator CPU Port (output latch) 16-bit timer (TM50) 8-bit timer/event counters (TM00 and TM01) 8-bit timer (TM02) Watch timer Watchdog timer Serial interface A/D converter LCD controller/driver Comparator External interrupt Oscillation enabled While the subsystem clock is not running HALT Mode Operation Status While Subsystem Clock Is Running While the main system clock is running While the main system clock is not running Does not run.
Operation stopped Remains in the state existing before the selection of HALT mode. Operation enabled Operation enabled Operation stopped Operation enabledNote 1
Operation enabled Operation enabled Operation enabled Operation enabled Operation stopped Operation enabled Operation enabledNote 5 Operation enabledNote 6
Operation enabledNote 2 Operation enabledNote 2
Operation enabled Operation enabled
Operation enabledNote 3 Operation enabledNote 3 Operation stopped Operation enabledNote 4
Operation enabledNote 2
Operation enabled
Operation enabledNote 3
Notes 1. Operation is enabled only when TI0 or TI1 is selected as the count clock. 2. Operation is enabled while the main system clock is selected. 3. Operation is enabled while the subsystem clock is selected. 4. Operation is enabled in both 3-wire serial I/O and UART modes while an external clock is being used. 5. Operation is enabled while TM02 is operating, or as an external interrupt. 6. Maskable interrupt that is not masked
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(2)
Releasing HALT mode The HALT mode can be released by the following three types of sources: (a) Releasing by unmasked interrupt request The HALT mode is released by an unmasked interrupt request. In this case, if interrupts are enabled to be acknowledged, vectored interrupt servicing is performed. instruction at the next address is executed. Figure 16-2. Releasing HALT Mode by Interrupt
HALT instruction Standby release signal Operation mode
If interrupts are disabled, the
Wait
HALT mode
Wait Oscillation
Operation mode
Clock
Remarks 1. The broken lines indicate the case where the interrupt request that has released the standby mode is acknowledged. 2. The wait time is as follows: * When vectored interrupt servicing is performed: * When vectored interrupt servicing is not performed: (b) Releasing by non-maskable interrupt request The HALT mode is released regardless of whether interrupts are enabled or disabled, and vectored interrupt servicing is performed. 9 to 10 clocks 1 to 2 clocks
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(c)
Releasing by RESET input When the HALT mode is released by the RESET signal, execution branches to the reset vector address in the same manner as the ordinary reset operation, and program execution is started. Figure 16-3. Releasing HALT Mode by RESET Input
HALT instruction RESET signal Operation mode Reset period
Oscillation stops
Wait (215/fX : 6.55 ms)
HALT mode Oscillation
Oscillation stabilization wait status Oscillation
Operation mode
Clock
Remarks 1. fX: Main system clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz. Table 16-2. Operation After Release of HALT Mode
Releasing Source Maskable interrupt request MKxx 0 0 1 Non-maskable interrupt request RESET input - --IE 0 1 x x - Operation Executes next address instruction Executes interrupt servicing Retains HALT mode Executes interrupt servicing Reset processing
x: Don't care
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16.2.2 STOP mode (1) Setting and operation status of STOP mode The STOP mode is set by executing the STOP instruction. Caution Because the standby mode can be released by an interrupt request signal, the standby mode is released as soon as it is set if there is an interrupt source whose interrupt request flag is set and interrupt mask flag is reset. When the STOP mode is set, therefore, the HALT mode is set immediately after the STOP instruction has been executed, the wait time set by the oscillation stabilization time selection register (OSTS) elapses, and then an operation mode is set. The operation status in the STOP mode is shown in the following table. Table 16-3. STOP Mode Operating Status
Item STOP Mode Operation Status While Main System Clock Is Running While the subsystem clock is running Main system clock generator CPU Port (output latch) 16-bit timer (TM50) 8-bit timer/event counter (TM00 and TM01) 8-bit timer (TM02) Watch timer Watchdog timer Serial interface A/D converter LCD controller/driver Comparator External interrupt Oscillation stopped Operation stopped Remains in the state existing before the selection of STOP mode. Operation stopped Operation enabledNote 1 While the subsystem clock is not running
Operation enabledNote 2 Operation enabledNote 2 Operation stopped Operation enabledNote 3 Operation stopped Operation enabledNote 2 Operation enabledNotes 5, 6 Operation enabledNote 4
Operation stopped Operation stopped
Operation stopped Operation enabledNote 6
Notes 1. Operation is enabled only when TI0 or TI1 is selected as the count clock. 2. Operation is enabled while the subsystem clock is selected. 3. Operation is enabled in both 3-wire serial I/O and UART modes while an external clock is being used. 4. Maskable interrupt that is not masked 5. Operation is enabled while TM02 is running. 6. Operation is enabled as an external interrupt.
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(2)
Releasing STOP mode The STOP mode can be released by the following two types of sources: (a) Releasing by unmasked interrupt request The STOP mode can be released by an unmasked interrupt request. In this case, if interrupts are enabled to be acknowledged, vectored interrupt servicing is performed, after the oscillation stabilization time has elapsed. If interrupts are disabled, the instruction at the next address is executed. Figure 16-4. Releasing STOP Mode by Interrupt
Wait (set time by OSTS)
STOP instruction Standby release signal Operation mode Oscillation
STOP mode Oscillation stops
Oscillation stabilization wait status Oscillation
Operation mode
Clock
Remark
The broken lines indicate the case where the interrupt request that has released the standby mode is acknowledged.
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(b)
Releasing by RESET input When the STOP mode is released by the RESET signal, the reset operation is performed after the oscillation stabilization time has elapsed. Figure 16-5. Releasing STOP Mode by RESET Input
STOP instruction RESET signal Operation mode Oscillation Reset period Oscillation stabilization wait status Oscillation Operation mode Wait (215/fX : 6.55 ms)
STOP mode Oscillation stops
Clock
Remarks 1. fX: Main system clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz. Table 16-4. Operation After Release of STOP Mode
Releasing Source Maskable interrupt request MKxx 0 0 1 RESET input - IE 0 1 x --Operation Executes next address instruction Executes interrupt servicing Retains STOP mode Reset processing
x: Don't care
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CHAPTER 17 RESET FUNCTION
The following two operations are available to generate reset signals. (1) External reset input via RESET pin (2) Internal reset by program loop time detected by the watchdog timer The external and internal resets have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H by RESET input. When a low level is input to the RESET pin or the watchdog timer overflows, a reset is applied and each hardware item is set to the status shown in Table 17-1. Each pin is high impedance during reset input or during the oscillation stabilization time just after reset release. When a high level is input to the RESET pin, the reset is released and program execution is started after the oscillation stabilization time (2 /fx) has elapsed. The reset applied by the watchdog timer overflow is automatically released after reset, and program execution is started after the oscillation stabilization time (2 /fx) has elapsed (see Figures 17-2 through 17-4). Cautions 1. For an external reset, input a low level for 10 s or more to the RESET pin. 2. When the STOP mode is released by reset, the STOP mode contents are held during reset input. However, the port pins become high impedance. Figure 17-1. Block Diagram of Reset Function
15 15
RESET
Reset controller
Reset signal
Count clock
Watchdog timer Stop
Overflow
Interrupt function
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Figure 17-2. Reset Timing by RESET Input
X1 During normal operation RESET Reset period (oscillation stops) Oscillation stabilization time wait Normal operation (reset processing)
Internal reset signal Delay Port pin Delay Hi-Z
Figure 17-3. Reset Timing by Overflow in Watchdog Timer
X1 During normal operation Overflow in watchdog timer Reset period (oscillation continues) Oscillation stabilization time wait Normal operation (reset processing)
Internal reset signal
Port pin
Hi-Z
Figure 17-4. Reset Timing by RESET Input in STOP Mode
X1 STOP instruction execution During normal Stop status operation (oscillation stops) RESET Oscillation stabilization time wait
Reset period (oscillation stops)
Normal operation (reset processing)
Internal reset signal Delay Port pin Delay Hi-Z
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Table 17-1. Hardware Status After Reset (1/2)
Hardware Program counter (PC)
Note 1
Status After Reset The contents of reset vector tables (0000H and 0001H) are set. Undefined 02H
Stack pointer (SP) Program status word (PSW) RAM Data memory General-purpose registers Ports (P0, P2, P4, P5, P8, and P9) (Output latch) Port mode registers (PM0, PM2, PM4, PM5, PM8, and PM9) Pull-up resistor option registers (PU0 to PU2) Processor clock control register (PCC) Suboscillation mode register (SCKM) Subclock control register (CSS) Oscillation stabilization time selection register (OSTS) 16-bit timer Timer counter (TM50) Compare register (CR50) Capture register (TCP50) Mode control register (TMC50) 8-bit timer/event counter Timer counters (TM00, TM01, and TM02) Compare registers (CR00, CR01, and CR02) Mode control registers (TMC00, TMC01, and TMC02) Watch timer Watchdog timer Mode control register (WTM) Timer clock selection register (TCL2) Mode register (WDTM) A/D converter Mode register (ADM0) A/D input selection register (ADS0) A/D conversion result register (ADCR0) Comparator Mode register (CMPRM0)
UndefinedNote 2 UndefinedNote 2 00H FFH 00H 02H 00H 00H 04H 0000H FFFFH Undefined 00H 00H Undefined 00H 00H 00H 00H 00H 00H Undefined 00H
Notes 1. During reset input and oscillation stabilization time wait, only the PC contents among the hardware statuses become undefined. All other hardware remains unchanged after reset. 2. The post-reset values are retained in the standby mode.
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Table 17-1. Hardware Status After Reset (2/2)
Hardware Serial interface Mode register (CSIM00) Asynchronous serial interface mode register (ASIM00) Asynchronous serial interface status register (ASIS00) Baud rate generator control register (BRGC00) Transmit shift register (TXS00) Receive buffer register (RXB00) LCD controller/driver LCD display mode register (LCDM0) LCD port selector (LPS0) LCD clock control register (LCDC0) Interrupts Request flag registers (IF0 and IF1) Mask flag registers (MK0 and MK1) External interrupt mode registers (INTM0 and INTM1) Key return mode register (KRM00) Status After Reset 00H 00H 00H 00H FFH Undefined 00H 00H 00H 00H FFH 00H 00H
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CHAPTER 18 PD78F9418A
The PD78F9418A is a version with the internal ROM of the mask ROM version replaced by flash memory. The differences between the PD78F9418A and the mask ROM versions are shown in Table 18-1. Table 18-1. Differences Between PD78F9418A and Mask ROM Versions
Item Flash Memory Version Mask ROM Version
PD78F9418A
PD789405A PD789415A
12 KB
PD789406A PD789416A
16 KB
PD789407A PD789417A
24 KB
Internal memory
ROM High-speed RAM LCD data RAM
32 KB (Flash memory) 512 bytes 28 bytes 32 (software control only) Not provided Not provided Provided
Pull-up resistor Divider resistor for LCD driving IC pin VPP pin Electrical specifications
36 (software control: 32, mask option control: 4) Can be specified on-chip by mask option Provided Not provided
Refer to CHAPTER 21 ELECTRICAL SPECIFICATIONS.
Cautions 1. There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing an application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask ROM version. 2. When A/D conversion result register 0 (ADCR0) is used as the 8-bit A/D converter (PD789407A Subseries), ADCR0 will be manipulated by an 8-bit memory manipulation instruction. When used as the 10-bit A/D converter (PD789417A Subseries), ADCR0 will be manipulated by a 16-bit memory manipulation instruction. However, when the PD78F9418A is used as the flash memory version of the PD789405A, 789406A, and 789407A, ADCR0 can be manipulated by an 8-bit memory manipulation instruction. In this case, use the object file assembled in the PD789405A, 789406A, and 789407A.
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18.1 Flash Memory Characteristics
Flash memory programming is performed by connecting a dedicated flash programmer (Flashpro III (part no. FLPR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4)) to the target system with the PD78F9418A mounted on the target system (on-board). A flash memory program adapter (FA adapter), which is a target board used exclusively for programming, is also provided. Remark FL-PR3, FL-PR4, and the program adapter are products made by Naito Densei Machida Mfg. Co., Ltd. (TEL +81-45-475-4191). Programming using flash memory has the following advantages. * Software can be modified after the microcontroller is solder-mounted on the target system. * Distinguishing software facilities small-quantity, varied model production * Easy data adjustment when starting mass production 18.1.1 Programming environment The following shows the environment required for PD78F9418A flash memory programming. When Flashpro III (part no. FL-PR3, PG-FP3) or Flashpro IV (part no. FL-PR4, PG-FP4) is used as a dedicated flash programmer, a host machine is required to control the dedicated flash programmer. Communication between the host machine and flash programmer is performed via RS-232C/USB (Rev. 1.1). For details, refer to the manuals for Flashpro III/Flashpro IV. Remark USB is supported by Flashpro IV only. Figure 18-1. Environment for Writing Program to Flash Memory
VPP RS-232C USB Dedicated flash programmer VDD VSS RESET 3-wire serial I/O, UART or pseudo 3-wire
PD78F9418A
Host machine
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18.1.2 Communication mode Use the communication mode shown in Table 18-2 to perform communication between the dedicated flash programmer and PD78F9418A. Table 18-2. Communication Mode List
Communication Mode TYPE SettingNote 1 COMM PORT SIO Clock CPU Clock In Flashpro 3-wire serial I/O SIO ch-0 100 Hz to (3-wire, sync.) 1.25 MHzNote 2 1, 2, 4, 5 MHzNotes 2, 3 5 MHzNote 5 On Target Board 1 to 5 MHzNote 2 Multiple Rate 1.0 SI/RxD/P22 SO/TxD/P21 SCK/ASCK/P20 RxD/SI/P22 TxD/SO/P21 Pins Used Number of VPP Pulses
0
UART
UART ch-0 (Async.)
4,800 to 76,800 bps
Notes 2, 4
4.91 or 5 MHzNote 2 1 to 5 MHzNote 2
1.0
8
Pseudo 3-wire
Port A (Pseudo3 wire) Port B (Pseudo3 wire)
100 Hz to 1 kHz
1, 2, 4, 5 MHzNotes 2, 3
1.0
P01 P02 P00 P40/KR0 P41/KR1 P42/KR2
12
13
Notes 1. Selection items for TYPE settings on the dedicated flash programmer (Flashpro III (part no. FL-PR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4)). 2. The possible setting range differs depending on the voltage. For details, refer to CHAPTER 21 ELECTRICAL SPECIFICATIONS. 3. 2 or 4 MHz only for Flashpro III 4. Because signal wave slew also affects UART communication, in addition to the baud rate error, thoroughly evaluate the slew and baud rate error. 5. Only for Flashpro IV. However, when using Flashpro III, be sure to select the clock of the resonator on the board. UART cannot be used with the clock supplied by Flashpro III. Figure 18-2. Communication Mode Selection Format
10 V VPP VDD VSS VPP pulses 1 2 n
VDD RESET VSS
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Figure 18-3. Example of Connection with Dedicated Flash Programmer (a) 3-wire serial I/O
Dedicated flash programmer VPP1 VDD RESET SCK SO SI CLKNote 1 GND VPP VDD0, VDD1 RESET SCK SI SO X1 VSS0, VSS1
PD78F9418A
(b) UART
Dedicated flash programmer VPP1 VDD RESET SO SI CLKNotes 1, 2 GND VPP VDD0, VDD1 RESET RXD TXD X1 VSS0, VSS1
PD78F9418A
(c) Pseudo 3-wire (when P0 is used)
Dedicated flash programmer VPP1 VDD RESET SCK SO SI CLK
Note 1
PD78F9418A
VPP VDD0, VDD1 RESET P00 (serial clock) P02 (serial input) P01 (serial output) X1 VSS0, VSS1
GND
Notes 1. Connect this pin when the system clock is supplied from the dedicated flash programmer. resonator is already connected to the X1 pin, do not connect to the CLK pin.
If a
2. When using UART with Flashpro III, the clock of the resonator connected to the X1 pin must be used, so do not connect to the CLK pin. Caution The VDD pin, if already connected to the power supply, must be connected to the VDD pin of the dedicated flash programmer. When using the power supply connected to the VDD pin, supply voltage before starting programming.
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If Flashpro III (part no. FL-PR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4) is used as a dedicated flash programmer, the following signals are generated for the PD78F9418A. For details, refer to the manual of Flashpro III/Flashpro IV. Table 18-3. Pin Connection List
Signal Name I/O Pin Function Pin Name 3-Wire Serial I/O UART Pseudo 3-Wire
VPP1 VPP2 VDD
Output - I/O - Output Output Input Output Output Input
Write voltage -
VPP -
x
Note
x
Note
x
Note
VDD voltage generation/ VDD0, VDD1 voltage monitoring Ground Clock output Reset signal Receive signal Transmit signal Transfer clock Handshake signal VSS0, VSS1 X1 RESET SO/TxD/P01/P41 SI/RxD/P02/P42 SCK/P00/P40 -
GND CLK RESET SI SO SCK HS
x x x x
Note VDD voltage must be supplied before programming is started. Remark : Pin must be connected. : If the signal is supplied on the target board, pin does not need to be connected. x: Pin does not need to be connected.
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18.1.3 On-board pin connections When programming on the target system, provide a connector on the target system to connect to the dedicated flash programmer. There may be cases in which an on-board function that switches from the normal operation mode to flash memory programming mode is required. Input 0 V to the VPP pin in the normal operation mode. A write voltage of 10.0 V (TYP.) is supplied to the VPP pin in the flash memory programming mode. Therefore, connect the VPP pin using method (1) or (2) below. (1) (2) Connect a pull-down resistor of RVPP = 10 k to the VPP pin. Set the jumper on the board to switch the input of VPP pin to the programmer side or directly to GND.
The following shows an example of VPP pin connection. Figure 18-4. VPP Pin Connection Example
PD78F9418A
Connection pin of dedicated flash programmer VPP Pull-down resistor (RVPP)
The following shows the pins used by each serial interface.
Serial Interface 3-wire serial I/O UART Pseudo 3-wire Pins Used SI, SO, SCK RxD, TxD P00, P01, P02 P40, P41, P42
Note that signal conflict or malfunction of other devices may occur when an on-board serial interface pin that is connected to another device is connected to the dedicated flash programmer.
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(1)
Signal conflict A signal conflict occurs if the dedicated flash programmer (output) is connected to a serial interface pin (input) connected to another device (output). To prevent this signal conflict, isolate the connection with the other device or put the other device in the output high impedance status. Figure 18-5. Signal Conflict (Serial Interface Input Pin)
PD78F9418A
Signal conflict Input pin Other device Output pin Connection pin of dedicated flash programmer
In the flash memory programming mode, the signal output by another device and the signal sent by the dedicated flash programmer conflict. To prevent this, isolate the signal on the device side.
(2)
Malfunction of another device When the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) connected to another device (input), a signal may be output to the device, causing a malfunction. To prevent such malfunction, isolate the connection with other device or set so that the input signal to the device is ignored. Figure 18-6. Malfunction of Another Device
PD78F9418A
Connection pin of dedicated flash programmer Pin Other device Input pin
If the signal output by the PD78F9418A affects another device in the flash memory programming mode, isolate the signal on the device side.
PD78F9418A
Connection pin of dedicated flash programmer Pin Other device Input pin
If the signal output by the dedicated flash programmer affects another device, isolate the signal on the device side.
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When the reset signal of the dedicated flash programmer is connected to the RESET pin connected to the reset signal generator on the board, a signal conflict occurs. To prevent this signal conflict, isolate the connection with the reset signal generator. If a reset signal is input from the user system in the flash memory programming mode, a normal programming operation will not be performed. programmer during this period. Figure 18-7. Signal Conflict (RESET Pin)
PD78F9418A
Signal conflict Connection pin of dedicated flash programmer Reset signal generator Output pin
Do not input signals other than reset signals from the dedicated flash
RESET
In the flash memory programming mode, the signal output by the reset signal generator and the signal output by the dedicated flash programmer conflict, therefore, isolate the signal on the reset signal generator side.
Shifting to the flash memory programming mode sets all the pins except those used for flash memory programming communication to the status immediately after reset. Therefore, if the external device does not acknowledge an initial status such as the output high impedance status, connect the external device to VDD0, VDD1, VSS0, or VSS1 via a resistor. When using an on-board clock, connection of X1, X2, XT1, and XT2 must conform to the methods in the normal operation mode. When using the clock output of the flash programmer, directly connect it to the X1 pin with the on-board main oscillator disconnected, and leave the X2 pin open. For the subclock, connection conforms to that in the normal operation mode. To use the power output of the flash programmer, connect the VDD0 and VDD1 pins to VDD of the flash programmer, and the VSS0 and VSS1 pins to GND of the flash programmer. To use the on-board power supply, connection must conform to that in the normal operation mode. However, because the voltage is monitored by the flash programmer, therefore, VDD of the flash programmer must be connected. For the other power supply pins (AVDD, AVREF, AVSS), supply the same power supply as in the normal operation mode. Handle the other pins (S0 to S15, COM0 to COM3, VLC0 to VLC2, BIAS) in the same way as in the normal operation mode.
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18.1.4 Connection when using flash memory writing adapter The following shows an example of the recommended connection when using the flash memory writing adapter. Figure 18-8. Example of Flash Memory Writing Adapter Connection When Using 3-Wire Serial I/O Mode
VDD (2.7 to 5.5 V) GND
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 1 59 2 58 3 57 4 56 5 55 6 54 7 53 8 52 9 51 10 PD78F9418A 50 11 49 12 48 13 47 14 46 15 45 16 44 17 43 18 42 19 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 GND VDD VDD2 (LVDD)
SI
SO
SCK
CLKOUT RESET VPP RESERVE/HS Writer interface
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CHAPTER 18 PD78F9418A
Figure 18-9. Example of Flash Memory Writing Adapter Connection When Using UART Mode
VDD (2.7 to 5.5 V) GND
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 1 59 2 58 3 57 4 56 5 55 6 54 7 53 8 52 9 51 10 PD78F9418A 50 11 49 12 48 13 47 14 46 15 45 16 44 17 43 18 42 19 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 GND VDD VDD2 (LVDD)
SI
SO
SCK
CLKOUT RESET VPP RESERVE/HS Writer interface
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Figure 18-10. Example of Flash Memory Writing Adapter Connection When Using Pseudo 3-Wire Mode (When P0 Is Used)
VDD (2.7 to 5.5 V) GND
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 1 59 2 58 3 57 4 56 5 55 6 54 7 53 8 52 9 51 10 PD78F9418A 50 11 49 12 48 13 47 14 46 15 45 16 44 17 43 18 42 19 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 GND VDD VDD2 (LVDD)
SI
SO
SCK
CLKOUT RESET VPP RESERVE/HS Writer interface
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CHAPTER 19 MASK OPTIONS
The mask ROM versions of the PD789407A and PD789417A Subseries have the following mask options. Caution The flash memory version does not have a mask option.
19.1 Mask Option for Pins
Table 19-1. Selection of Mask Option for Pins
Pin P50 to P53 Mask Option Whether a pull-up resistor is to be incorporated can be specified in 1-bit units.
For P50 to P53 (port 5), a mask option is used to specify whether a pull-up resistor is to be incorporated. The mask option is selectable in 1-bit units.
19.2 Mask Option for Voltage Division Resistor for LCD Driver
A mask option is used to specify whether a voltage division resistor is to be incorporated for the LCD driver, as listed below: Table 19-2. Combination of Selectable Voltage Division Resistor
RLC1 (2 x RLC2) None RLC2 None 10 k 100 k - 20 k - 200 k - -
: Selectable -: Not selectable
VDD LIPS0 P-ch BIAS RLC1
VLC0
RLC2
VLC1 VLCD
RLC2
VLC2
RLC2
VSS
LIPS0: Bit 4 of LCD display mode register 0 (LCDM0)
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CHAPTER 20 INSTRUCTION SET
This chapter lists the instruction set of the PD789407A and 789417A Subseries. For details of the operation and machine language (instruction code) of each instruction, refer to 78K/0S Series Instructions User's Manual (U11047E).
20.1 Operation
20.1.1 Operand identifiers and description methods Operands are described in the Operands column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for details). When there are two or more description methods, select one of them. Uppercase letters and the symbols #, !, $, and [ ] are keywords and are described as they are. Each symbol has the following meaning. * #: Immediate data specification * !: Absolute address specification * $: Relative address specification * [ ]: Indirect address specification
In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to describe the #, !, $ and [ ] symbols. For operand register identifiers r and rp, either functional names (X, A, C, etc.) or absolute names (names in parentheses in the table below, R0, R1, R2, etc.) can be used for description. Table 20-1. Operand Identifiers and Description Methods
Identifier r rp sfr saddr saddrp addr16 addr5 word byte bit Description Method X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7) AX (RP0), BC (RP1), DE (RP2), HL (RP3) Special function register symbol FE20H to FF1FH Immediate data or label FE20H to FF1FH Immediate data or label (even addresses only) 0000H to FFFFH Immediate data or label (only even addresses for 16-bit data transfer instructions) 0040H to 007FH Immediate data or label (even addresses only) 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label
Remark
See Table 3-3 for symbols of special function registers.
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20.1.2 Description of "Operation" column A: X: B: C: D: E: H: L: AX: BC: DE: HL: PC: SP: PSW: CY: AC: Z: IE: NMIS: ( ): : : V: : jdisp8: A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer Program status word Carry flag Auxiliary carry flag Zero flag Interrupt request enable flag Flag indicating non-maskable interrupt servicing in progress Memory contents indicated by address or register contents in parenthesis Logical product (AND) Logical sum (OR) Exclusive logical sum (exclusive OR) Inverted data Signed 8-bit data (displacement value)
XH, XL: Higher 8 bits and lower 8 bits of 16-bit register
addr16: 16-bit immediate data or label
20.1.3 Description of "Flag" column (Blank): Unchanged 0: 1: x: R: Cleared to 0 Set to 1 Set/cleared according to the result Previously saved value is restored
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20.2 Operation List
Mnemonic Operands Bytes Clocks Operation Flag Z AC CY MOV r, #byte saddr, #byte sfr, #byte A, r r, A
Note 1
3 3 3 2 2 2 2 2 2 3 3 3 2 2 1 1 1 1 2 2 1 2 2 2 1 1 2
6 6 6 4 4 4 4 4 4 8 8 6 4 4 6 6 6 6 6 6 4 6 6 6 8 8 8
r byte (saddr) byte sfr byte Ar rA A (saddr) (saddr) A A sfr sfr A A (addr16) (addr16) A PSW byte A PSW PSW A A (DE) (DE) A A (HL) (HL) A A (HL + byte) (HL + byte) A AX Ar A (saddr) A sfr A (DE) A (HL) A (HL + byte) x x x x x x
Note 1
A, saddr saddr, A A, sfr sfr, A A, !addr16 !addr16, A PSW, #byte A, PSW PSW, A A, [DE] [DE], A A, [HL] [HL], A A, [HL+byte] [HL+byte], A XCH A, X A, r
Note 2
A, saddr A, sfr A, [DE] A, [HL] A, [HL+byte]
Notes 1. Except r = A. 2. Except r = A, X. Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC).
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Mnemonic
Operands
Bytes
Clocks
Operation
Flag Z AC CY
MOVW
rp, #word AX, saddrp saddrp, AX AX, rp rp, AX
Note
3 2 2 1 1 1 2 3 2 2 3 1 2 2 3 2 2 3 1 2 2 3 2 2 3 1 2
6 6 8 4 4 8 4 6 4 4 8 6 6 4 6 4 4 8 6 6 4 6 4 4 8 6 6
rp word AX (saddrp) (saddrp) AX AX rp rp AX AX rp A, CY A + byte (saddr), CY (saddr) + byte A, CY A + r A, CY A + (saddr) A, CY A + (addr16) A, CY A + (HL) A, CY A + (HL + byte) A, CY A + byte + CY (saddr), CY (saddr) + byte + CY A, CY A + r + CY A, CY A + (saddr) + CY A, CY A + (addr16) + CY A, CY A + (HL) + CY A, CY A + (HL + byte) + CY A, CY A - byte (saddr), CY (saddr) - byte A, CY A - r A, CY A - (saddr) A, CY A - (addr16) A, CY A - (HL) A, CY A - (HL + byte) x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
Note
XCHW ADD
AX, rp
Note
A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL+byte]
ADDC
A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL+byte]
SUB
A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL+byte]
Note Only when rp = BC, DE, or HL. Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC).
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Mnemonic
Operands
Bytes
Clocks
Operation
Flag Z AC CY
SUBC
A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL+byte]
2 3 2 2 3 1 2 2 3 2 2 3 1 2 2 3 2 2 3 1 2 2 3 2 2 3 1 2
4 6 4 4 8 6 6 4 6 4 4 8 6 6 4 6 4 4 8 6 6 4 6 4 4 8 6 6
A, CY A - byte - CY (saddr), CY (saddr) - byte - CY A, CY A - r - CY A, CY A - (saddr) - CY A, CY A - (addr16) - CY A, CY A - (HL) - CY A, CY A- (HL + byte) - CY A A byte (saddr) (saddr) byte AAr A A (saddr) A A (addr16) A A (HL) A A (HL + byte) A A byte (saddr) (saddr) byte AAr A A (saddr) A A (addr16) A A (HL) A A (HL + byte) A A V byte (saddr) (saddr) V byte AAVr A A V (saddr) A A V (addr16) A A V (HL) A A V (HL + byte)
x x x x x x x x x x x x x x x x x x x x x x x x x x x x
x x x x x x x
x x x x x x x
AND
A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL+byte]
OR
A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL+byte]
XOR
A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL+byte]
Remark
One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC).
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Mnemonic
Operands
Bytes
Clocks
Operation
Flag Z AC CY
CMP
A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL+byte]
2 3 2 2 3 1 2 3 3 3 2 2 2 2 1 1 1 1 1 1 3 3 2 3 2 3 3 2 3 2 1 1 1
4 6 4 4 8 6 6 6 6 6 4 4 4 4 4 4 2 2 2 2 6 6 4 6 10 6 6 4 6 10 2 2 2
A - byte (saddr) - byte A-r A - (saddr) A - (addr16) A - (HL) A - (HL + byte) AX, CY AX + word AX, CY AX - word AX - word rr+1 (saddr) (saddr) + 1 rr-1 (saddr) (saddr) - 1 rp rp + 1 rp rp - 1 (CY, A7 A0, Am-1 Am) x 1 (CY, A0 A7, Am+1 Am) x 1 (CY A0, A7 CY, Am-1 Am) x 1 (CY A7, A0 CY, Am+1 Am) x 1 (saddr.bit) 1 sfr.bit 1 A.bit 1 PSW.bit 1 (HL).bit 1 (saddr.bit) 0 sfr.bit 0 A.bit 0 PSW.bit 0 (HL).bit 0 CY 1 CY 0 CY CY
x x x x x x x x x x x x x x
x x x x x x x x x x x x x x
x x x x x x x x x x
ADDW SUBW CMPW INC
AX, #word AX, #word AX, #word r saddr
DEC
r saddr
INCW DECW ROR ROL RORC ROLC SET1
rp rp A, 1 A, 1 A, 1 A, 1 saddr.bit sfr.bit A.bit PSW.bit [HL].bit
x x x x
x
x
x
CLR1
saddr.bit sfr.bit A.bit PSW.bit [HL].bit
x
x
x
SET1 CLR1 NOT1
CY CY CY
1 0 x
Remark
One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC).
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CHAPTER 20 INSTRUCTION SET
Mnemonic
Operands
Bytes
Clocks
Operation
Flag Z AC CY
CALL
!addr16
3
6
(SP - 1) (PC + 3)H, (SP - 2) (PC + 3)L, PC addr16, SP SP - 2 (SP - 1) (PC + 1)H, (SP - 2) (PC + 1)L, PCH (00000000, addr5 + 1), PCL (00000000, addr5), SP SP - 2 PCH (SP + 1), PCL (SP), SP SP + 2 PCH (SP + 1), PCL (SP), PSW (SP + 2), SP SP + 3, NMIS 0 (SP - 1) PSW, SP SP - 1 (SP - 1) rpH, (SP - 2) rpL, SP SP - 2 PSW (SP), SP SP + 1 rpH (SP + 1), rpL (SP), SP SP + 2 SP AX AX SP PC addr16 PC PC + 2 + jdisp8 PCH A, PCL X PC PC + 2 + jdisp8 if CY = 1 PC PC + 2 + jdisp8 if CY = 0 PC PC + 2 + jdisp8 if Z = 1 PC PC + 2 + jdisp8 if Z = 0 PC PC + 4 + jdisp8 if (saddr.bit) = 1 PC PC + 4 + jdisp8 if sfr.bit = 1 PC PC + 3 + jdisp8 if A.bit = 1 PC PC + 4 + jdisp8 if PSW.bit = 1 PC PC + 4 + jdisp8 if (saddr.bit) = 0 PC PC + 4 + jdisp8 if sfr.bit = 0 PC PC + 3 + jdisp8 if A.bit = 0 PC PC + 4 + jdisp8 if PSW.bit = 0 B B-1, then PC PC + 2 + jdisp8 if B 0 C C-1, then PC PC + 2 + jdisp8 if C 0 (saddr) (saddr) - 1, then PC PC + 3 + jdisp8 if (saddr) 0 No Operation IE 1 (Enable interrupt) IE 0 (Disable interrupt) Set HALT mode Set STOP mode R R R R R R
CALLT
[addr5]
1
8
RET RETI
1 1
6 8
PUSH
PSW rp
1 1 1 1 2 2 3 2 1 2 2 2 2 4 4 3 4 4 4 3 4 2 2 3
2 4 4 6 8 6 6 6 6 6 6 6 6 10 10 8 10 10 10 8 10 6 6 8
POP
PSW rp
MOVW
SP, AX AX, SP
BR
!addr16 $addr16 AX
BC BNC BZ BNZ BT
$saddr16 $saddr16 $saddr16 $saddr16 saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16
BF
saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16
DBNZ
B, $addr16 C, $addr16 saddr, $addr16
NOP EI DI HALT STOP
1 3 3 1 1
2 6 6 2 2
Remark
One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC).
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20.3 Instructions Listed by Addressing Type
(1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH, POP, DBNZ
2nd Operand 1st Operand
A
#byte
A
r
sfr
saddr
!addr16
PSW
[DE]
[HL]
[HL+byte] $addr16
1
None
ADD ADDC SUB SUBC AND OR XOR CMP
MOVNote MOV XCHNote XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
MOV ADD ADDC SUB SUBC AND OR XOR CMP
MOV
MOV XCH
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
ROR ROL RORC ROLC
r
MOV
INC DEC DBNZ
B, C sfr saddr MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV
DBNZ
INC DEC
!addr16 PSW MOV
MOV MOV PUSH POP
[DE] [HL] [HL+byte]
MOV MOV MOV
Note Except r = A.
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(2)
16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd Operand 1st Operand AX ADDW SUBW CMPW MOVW MOVWNote MOVW XCHW MOVW MOVW #word AX rpNote saddrp SP None
rp
INCW DECW PUSH POP
saddrp SP
MOVW MOVW
Note Only when rp = BC, DE, or HL. (3) Bit manipulation instructions SET1, CLR1, NOT1, BT, BF
2nd Operand 1st Operand A.bit BT BF BT BF BT BF BT BF SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 NOT1 $addr16 None
sfr.bit
saddr.bit
PSW.bit
[HL].bit
CY
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CHAPTER 20 INSTRUCTION SET
(4)
Call instructions/branch instructions CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ
2nd Operand 1st Operand Basic Instructions BR CALL BR CALLT BR BC BNC BZ BNZ DBNZ AX !addr16 [addr5] $addr16
Compound Instructions
(5)
Other instructions RET, RETI, NOP, EI, DI, HALT, STOP
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CHAPTER 21 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C)
Parameter Supply voltage Symbol VDD AVDD AVREF VPP Input voltage VI1 VI2 Output voltage Output current, high VO IOH 1 pin Total for all pins Output current, low IOL 1 pin Total for all pins Operating ambient temperature Storage temperature TA In normal operation mode During flash memory programming Tstg Mask ROM version Conditions AVDD - 0.3 V VDD AVDD + 0.3 V AVREF VDD + 0.3 V AVREF AVDD + 0.3 V Ratings -0.3 to +6.5 Unit V
PD78F9418A only Note
Pins other than P50 to P53 P50 to P53 N-ch open drain
-0.3 to +10.5 -0.3 to VDD + 0.3 -0.3 to +13 -0.3 to VDD + 0.3 -10 -30 30 160 -40 to +85 10 to 40 -65 to +150 -40 to +125
V V V V mA mA mA mA C C C C
PD78F9418A
Note Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash memory is written. * When supply voltage rises VPP must exceed VDD 10 s or more after VDD has reached the lower-limit value (1.8 V) of the operating voltage range (see a in the figure below). * When supply voltage drops VDD must be lowered 10 s or more after VPP falls below the lower-limit value (1.8 V) of the operating voltage range of VDD (see b in the figure below).
1.8 V 0V a b
VDD
VPP 1.8 V 0V
Caution
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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CHAPTER 21 ELECTRICAL SPECIFICATIONS
Main System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Resonator Ceramic resonator Recommended Circuit
VSS0 X1 X2
Parameter Oscillation frequency Note 1 (fX) Oscillation stabilization Note 2 time Oscillation frequency Note 1 (fX) Oscillation stabilization Note 2 time
Conditions VDD = Oscillation voltage range After VDD has reached MIN. of oscillation start voltage
MIN. 1.0
TYP.
MAX. 5.0
Unit MHz
C1
C2
4
ms
Crystal resonator
VSS0 X1
X2
1.0
5.0
MHz
C1
C2
VDD = 4.5 to 5.5 V VDD = 1.8 to 5.5 V 1.0
10 30 5.0
ms ms MHz
External clock
X1
X2
X1 input frequency Note 1 (fX) X1 input high-/low-level widths (tXH, tXL) X1 input frequency Note 1 (fX) X1 input high-/low-level widths (tXH, tXL) VDD = 2.7 to 5.5 V
85
500
ns
X1
X2
1.0
5.0
MHz
VDD = 2.7 to 5.5 V
85
500
ns
OPEN
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. oscillation is stabilized within the oscillation wait time. Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS0. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. Use a resonator whose
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CHAPTER 21 ELECTRICAL SPECIFICATIONS
Subsystem Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Resonator Crystal resonator Recommended Circuit
VSS0 XT1 XT2 R C4
Parameter Oscillation frequency Note 1 (fXT) Oscillation stabilization Note 2 time XT1 input frequency Note 1 (fXT) XT1 input high-/lowlevel widths (tXTH, tXTL)
Conditions
MIN. 32
TYP. 32.768
MAX. 35
Unit kHz
C3
VDD = 4.5 to 5.5 V VDD = 1.8 to 5.5 V 32
1.2
2 10 35
s s kHz
External clock
XT1
XT2
14.3
15.6
s
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. oscillation is stabilized within the oscillation wait time. Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS0. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. Use a resonator whose
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DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (1/3)
Parameter Output current, high Output current, low Input voltage, high Symbol IOH Per pin Total for all pins IOL Per pin Total for all pins VIH1 P00 to P03, P46, P47, P60 to P66, VDD = 2.7 to 5.5 V P80 to P87, P90 to P93 VDD = 1.8 to 5.5 V P50 to P53 N-ch open drain VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V On-chip pull-up resistor VIH3 VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V 0.7VDD 0.9VDD 0.7VDD 0.9VDD 0.7VDD 0.9VDD 0.8VDD 0.9VDD VDD - 0.1 0 0 0 0 0 0 0 VDD - 1.0 VDD - 0.5 1.0 0.5 1.0 0.4 3 Conditions MIN. TYP. MAX. -1 -15 10 80 VDD VDD 12 12 VDD VDD VDD VDD VDD 0.3VDD 0.1VDD 0.3VDD 0.1VDD 0.2VDD 0.1VDD 0.1 Unit mA mA mA mA V V V V V V V V V V V V V V V V V V V V V V
VIH2
RESET, P20 to P27, P40 to P45 VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V
VIH4 Input voltage, low VIL1
X1, X2, XT1, XT2
VDD = 1.8 to 5.5 V
P00 to P03, P46, P47, P60 to P66, VDD = 2.7 to 5.5 V P80 to P87, P90 to P93 VDD = 1.8 to 5.5 V P50 to P53 VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V
VIL2
VIL3
RESET, P20 to P27, P40 to P45 VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V
VIL4 Output voltage, high Output voltage, low VOH
X1, X2, XT1, XT2 IOH = -1 mA IOH = -100 A Pins other than P50 to P53
VDD = 1.8 to 5.5 V VDD = 4.5 to 5.5 V VDD = 1.8 to 5.5 V VDD = 4.5 to 5.5 V IOL = 10 mA VDD = 1.8 to 5.5 V IOL = 400 A
VOL1
VOL2
P50 to P53
VDD = 4.5 to 5.5 V IOL = 10 mA VDD = 1.8 to 5.5 V IOL = 1.6 mA
Input leakage current, high
ILIH1
VIN = VDD
Pins other than P50 to P53 (N-ch open drain), X1, X2, XT1, and XT2 X1, X2, XT1, XT2
A
ILIH2 ILIH3 Input leakage current, low ILIL1 VIN = 12 V VIN = 0 V
20 20 -3
A A A
P50 to P53 (N-ch open drain) Pins other than P50 to P53 (N-ch open drain), X1, X2, XT1, and XT2 X1, X2, XT1, XT2 P50 to P53 (N-ch open drain)
ILIL2 ILIL3
-20 -3
Note
A A
Note A low-level input leakage current of -30 A (MAX.) flows only during the 1-cycle time after a read instruction is executed to P50 to P53 when on-chip pull-up resistors are not connected to P50 to P53 (specified by mask option) and P50 to P53 are set to input mode. At times other than this, a -3 A (MAX.) current flows. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (2/3)
Parameter Output leakage current, high Output leakage current, low Symbol ILOH VOUT = VDD Conditions MIN. TYP. MAX. 3 -3 50 100 200 Unit
A A
k
ILOL
VOUT = 0 V
Software pull-up R1 resistor Mask option pull- R2 up resistorNote 1 Supply current (mask ROM version) IDD1Note 2
VIN = 0 V, pins other than P50 to P53
VIN = 0 V, P50 to P53 VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% TA = 25C VDD = 2.0 V 10%
Note 5 Note 6 Note 6 Note 5 Note 6 Note 6
15
30
60
k
5.0 MHz crystal oscillation operating mode (C1 = C2 = 22 pF) 5.0 MHz crystal oscillation HALT mode (C1 = C2 = 22 pF) 32.768 kHz crystal oscillation Note 4 operating mode (C3 = C4 = 22 pF, R1 = 220 k)
2.0 0.6 0.3 1.1 0.4 0.2 30 9 4 25 5 2.5 0.1 0.05 0.05 0.05 2.6 1.2 0.9
4.0 1.2 0.6 2.2 0.8 0.4 90 50 25 55 25 12.5 10 5.0 3.0 3.0 6.0 3.6 2.7
mA mA mA mA mA mA
IDD2
Note 2
IDD3
Note 2
A A A A A A A A A A
mA mA mA
IDD4
Note 2
32.768 kHz crystal oscillation HALT Note 4 mode (C3 = C4 = 22 pF, R1 = 220 k)
IDD5
Note 2
32.768 kHz crystal oscillation STOP mode
IDD6
Note 3
5.0 MHz crystal oscillation A/D operating mode (C1 = C2 = 22 pF)
VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10%
Notes 1. Mask ROM version only 2. The current flowing to AVREF (A/D operation ON (ADCS0 = 1)), AVDD current, and the port current (including the current flowing through the on-chip pull-up resistors) is not included. 3. The current flowing to AVREF (A/D operation ON (ADCS0 = 1)) and the port current (including the current flowing through the on-chip pull-up resistors) is not included. For the current flowing to AVREF, refer to the parameter of "Resistance between AVREF and AVSS" in the 8-Bit A/D Converter Characteristics and 10-Bit A/D Converter Characteristics. 4. When the main system clock is stopped 5. High-speed mode operation (when processor clock control register (PCC) is set to 00H) 6. Low-speed mode operation (when PCC is set to 02H) Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (3/3)
Parameter Symbol
Note 1
Conditions 5.0 MHz crystal oscillation operating mode (C1 = C2 = 22 pF) 5.0 MHz crystal oscillation HALT mode (C1 = C2 = 22 pF) 32.768 kHz crystal oscillation Note 3 operating mode (C3 = C4 = 22 pF, R1 = 220 k) VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% TA = 25C VDD = 2.0 V 10%
Note 4 Note 5 Note 5 Note 4 Note 5 Note 5
MIN.
TYP. 5.0 2.0 1.5 2.0 1.0 0.7 200 150 100 50 30 20 0.1 0.05 0.05 0.05
MAX. 14.0 5.0 3.0 6.0 3.0 2.0 600 450 300 150 90 60 10 5.0 3.0 3.0 16.0 7.0 5.0
Unit mA mA mA mA mA mA
Supply current IDD1 (PD78F9418A)
IDD2
Note 1
IDD3
Note 1
A A A A A A A A A A
mA mA mA
IDD4
Note 1
32.768 kHz crystal oscillation HALT Note 3 mode (C3 = C4 = 22 pF, R1 = 220 k)
IDD5
Note 1
32.768 kHz crystal oscillation STOP mode
IDD6
Note 2
5.0 MHz crystal oscillation A/D operating mode (C1 = C2 = 22 pF)
VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10%
Note 4 Note 5 Note 5
6.0 3.0 2.5
Notes 1. The current flowing to AVREF (A/D operation ON (ADCS0 = 1)), AVDD current, and the port current (including the current flowing through the on-chip pull-up resistors) is not included. 2. The current flowing to AVREF (A/D operation ON (ADCS0 = 1)) and the port current (including the current flowing through the on-chip pull-up resistors) is not included. For the current flowing to AVREF, refer to the parameter of "Resistance between AVREF and AVSS" in the 8-Bit A/D Converter Characteristics and 10-Bit A/D Converter Characteristics. 3. When the main system clock is stopped 4. High-speed mode operation (when processor clock control register (PCC) is set to 00H) 5. Low-speed mode operation (when PCC is set to 02H) Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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LCD Characteristics (TA = -40 to +85C, VDD = 2.2 to 5.5 V)
Parameter LCD drive voltage Symbol VLCD VAON0 = 1 VAON0 = 0
Note 1
Conditions
MIN. 2.2
TYP.
MAX. VDD VDD VDD
Unit V V V k k V
At 1/3 bias At 1/2 bias
2.7 3.0 100 10 0 200 20
LCD divider Note 2 resistor
RLCD
When selecting 100 k by mask option When selecting 10 k by mask option IO = 5 A IO = 1 A VLCD0 = VLCD VLCD1 = VLCD x 2/3 2.2 V VLCD VDD Note 1 VLCD2 = VLCD x 1/3
400 40 0.2 0.2
VODC LCD output voltage Note 3 (common) deviation VODS LCD output voltage Note 3 (segment) deviation
0
V
Notes 1. TA = -10 to +85C in the normal mode (VAON0 = 0) 2. For mask ROM version, 10 k, 100 k, or no divider resistor can be selected by mask option. The
PD78F9418A has no divider resistor.
3. Voltage deviation is the voltage difference between the ideal value of the segment or common output (VLCDn: n = 0 to 2) and the output voltage. Flash Memory Write/Erase Characteristics (PD78F9418A only) (TA = 10 to 40C, VDD = 1.8 to 5.5 V, in 5.0 MHz crystal oscillation operating mode)
Parameter Write current (VDD pin)
Note
Symbol IDDW
Conditions When VPP supply voltage = VPP1
MIN.
TYP.
MAX. 18
Unit mA
Write currentNote (VPP pin) Erase currentNote (VDD pin) Erase currentNote (VPP pin) Unit erase time Total erase time Write count VPP supply voltage
IPPW
When VPP supply voltage = VPP1
22.5
mA
IDDE
When VPP supply voltage = VPP1
18
mA
IPPE
When VPP supply voltage = VPP1
115
mA
ter tera Erase/write are regarded as 1 cycle VPP0 VPP1 In normal operation During flash memory programming
0.5
1
1 20 20
s s Times V V
0 9.7 10.0
0.2VDD 10.3
Note
The current flowing to the ports (including the current flowing through the on-chip pull-up resistors) is not included.
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CHAPTER 21 ELECTRICAL SPECIFICATIONS
AC Characteristics (1) Basic operation (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Cycle time (minimum instruction execution time) TI0, TI1 input frequency TI0, TI1 input high-/ low-level widths Interrupt input high-/ low-level widths RESET input low-level width Symbol TCY Operating with main system clock Conditions VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V MIN. 0.4 1.6 114 0 0 0.1 1.8 10 122 TYP. MAX. 8 8 125 4 275 Unit
s s s
MHz kHz
Operating with subsystem clock fTI VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V tTIH, tTIL VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V tINTH, tINTL tRSL INTP0 to INTP3
s s s s
10
TCY vs VDD (Main system clock)
60
10
Cycle time [ s]
Guaranteed operating range 1.0
0.4
0.1 1 2 3 4 5 6 Supply voltage VDD [V]
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(2) Serial interface (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (a) 3-wire serial I/O mode (SCK ... Internal clock output)
Parameter SCK cycle time Symbol tKCY1 VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V SCK high-/low-level widths SI setup time (to SCK) SI hold time (from SCK) SO output delay time from SCK tKH1, tKL1 tSIK1 VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V tKSI1 VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V tKSO1 R = 1 k, Note C = 100 pF VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V Conditions MIN. 800 3200 tKCY1/2-50 tKCY1/2-150 150 500 400 600 0 0 250 1000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns
Note R and C are the load resistance and load capacitance of the SO output line. (b) 3-wire serial I/O mode (SCK ... External clock input)
Parameter SCK cycle time Symbol tKCY2 VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V SCK high-/low-level widths SI setup time (to SCK) SI hold time (from SCK) SO output delay time from SCK tKH2, tKL2 tSIK2 VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V tKSI2 VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V tKSO2 R = 1 k, Note C = 100 pF VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V Conditions MIN. 900 3500 400 1600 100 150 400 600 0 0 300 1000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns
Note R and C are the load resistance and load capacitance of the SO output line. (c) UART mode (dedicated baud rate generator output)
Parameter Transfer rate Symbol VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V Conditions MIN. TYP. MAX. 78125 19531 Unit bps bps
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CHAPTER 21 ELECTRICAL SPECIFICATIONS
(d) UART mode (external clock input)
Parameter ASCK cycle time Symbol tKCY3 VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V ASCK high-/low-level widths Transfer rate tKH3, tKL3 VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V ASCK rise/fall times tR, tF Conditions MIN. 900 3500 400 1600 39063 9766 1 TYP. MAX. Unit ns ns ns ns bps bps
s
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CHAPTER 21 ELECTRICAL SPECIFICATIONS
AC Timing Test Points (Excluding X1 and XT1 Inputs)
0.8VDD 0.2VDD
Test points
0.8VDD 0.2VDD
Clock Timing
1/fX tXL tXH VIH4 (MIN.) VIL4 (MAX.)
X1 input
1/fXT tXTL tXTH VIH4 (MIN.) VIL4 (MAX.)
XT1 input
TI Timing
1/fTI tTIL tTIH
TI0, TI1
Interrupt Input Timing
tINTL tINTH
INTP0 to INTP3
RESET Input Timing
tRSL
RESET
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CHAPTER 21 ELECTRICAL SPECIFICATIONS
Serial Transfer Timing 3-wire serial I/O mode:
tKCYm tKLm tKHm
SCK
tSIKm SI
tKSIm
Input data
tKSOm
SO
Output data
Remark m = 1 or 2 UART mode (external clock input):
tKCY3 tKL3 tR ASCK tKH3 tF
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CHAPTER 21 ELECTRICAL SPECIFICATIONS
8-Bit A/D Converter Characteristics (PD789405A, 789406A, 789407A) (TA = -40 to +85C, 1.8 V AVREF AVDD = VDD 5.5 V, AVSS = VSS = 0 V)
Parameter Resolution Overall error
Note
Symbol
Conditions
MIN. 8
TYP. 8 0.4 0.8
MAX. 8 0.6 1.2 100 100 AVREF AVDD
Unit bit %FSR %FSR
2.7 V AVREF AVDD 5.5 V 2.7 V AVREF AVDD 5.5 V
Conversion time
tCONV
14 28
s s
V V k
Analog input voltage Reference voltage Resistance between AVREF and AVSS
VIAN AVREF RADREF
0 1.8 20 40
Note Excludes quantization error (0.2%FSR). Remark FSR: Full-scale range 10-Bit A/D Converter Characteristics (PD789415A, 789416A, 789417A, 78F9418A) (TA = -40 to +85C, 1.8 V AVREF AVDD = VDD 5.5 V, AVSS = VSS = 0 V)
Parameter Resolution Overall error
Note
Symbol
Conditions
MIN. 10
TYP. 10 0.2 0.4 0.8
MAX. 10 0.4 0.6 1.2 100 100 100 0.4 0.6 1.2 0.4 0.6 1.2 2.5 4.5 8.5 1.5 2.0 3.5
Unit bit %FSR %FSR %FSR
4.5 V AVREF AVDD 5.5 V 2.7 V AVREF AVDD 5.5 V 1.8 V AVREF AVDD 5.5 V 4.5 V AVREF AVDD 5.5 V 2.7 V AVREF AVDD 5.5 V 1.8 V AVREF AVDD 5.5 V
Note
Conversion time
tCONV
14 14 28
s s s
%FSR %FSR %FSR %FSR %FSR %FSR LSB LSB LSB LSB LSB LSB V V k
Zero-scale error
AINL
4.5 V AVREF AVDD 5.5 V 2.7 V AVREF AVDD 5.5 V 1.8 V AVREF AVDD 5.5 V
Full-scale error
Note
AINL
4.5 V AVREF AVDD 5.5 V 2.7 V AVREF AVDD 5.5 V 1.8 V AVREF AVDD 5.5 V
Non-integral linearity
Note
INL
4.5 V AVREF AVDD 5.5 V 2.7 V AVREF AVDD 5.5 V 1.8 V AVREF AVDD 5.5 V
Non-differential linearity
Note
DNL
4.5 V AVREF AVDD 5.5 V 2.7 V AVREF AVDD 5.5 V 1.8 V AVREF AVDD 5.5 V
Analog input voltage Reference voltage Resistance between AVREF and AVSS
VIAN AVREF RADREF
0 1.8 20 40
AVREF AVDD
Note
Excludes quantization error (0.05%FSR).
Remark FSR: Full-scale range
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Comparator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Analog input range Reference voltage input range Symbol VCIN VCREF VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V Accuracy Conditions MIN. 0 1.35 1.35 1.6 1.4 TYP. MAX. VDD 1.85 1.45 100 Unit V V V mV
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C)
Parameter Data retention power supply voltage Release signal set time Oscillation stabilization wait time
Note 1
Symbol VDDDR tSREL tWAIT
Conditions
MIN. 1.8 0
TYP.
MAX. 5.5
Unit V
s
2 /fX Note 2
15
Release by RESET Release by interrupt request
ms ms
Notes 1. The oscillation stabilization wait time is the time after oscillation has started during which the CPU is stopped to prevent unstable operation. 2. Selection of 2 /fX, 2 /fX, or 2 /fX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time selection register (OSTS). Remark fx: Main system clock oscillation frequency
12 15 17
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Data Retention Timing (STOP Mode Release by RESET)
Internal reset operation HALT mode STOP mode Data retention mode Operation mode
VDD
VDDDR STOP instruction execution
tSREL
RESET
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT mode STOP mode Data retention mode Operation mode
VDD
VDDDR STOP instruction execution
tSREL
Standby release signal (interrupt request) tWAIT
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CHAPTER 22 CHARACTERISTICS CURVES (REFERENCE VALUES)
22.1 Characteristics Curves for Mask ROM Versions
(TA = 25C) 10.0
PCC = 00H
1.0
PCC = 02H PCC = 00H (HALT mode) PCC = 02H (HALT mode)
0.5
Supply current IDD (mA)
0.1
0.05
Subsystem clock operation mode (CSS0 = 1) Subsystem clock operation HALT mode (CSS0 = 1)
0.01
0.005
X1 X2 XT1 XT2 Crystal resonator Crystal resonator 5.0 MHz 32.768 kHz 220 k 22 pF 22 pF VSS 33 pF VSS 33 pF
0.001 0 1 2 3 4 5 6 7 8 Supply voltage VDD (V)
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IOH vs VDD - VOH
(TA = 25C) 20
High-level output current IOH (mA)
IOL vs VOL
(TA = 25C) 30
Low-level output current IOL (mA)
VDD = 5.5 V VDD = 3.5 V VDD = 3.0 V
VDD = 5.5 V
VDD = 3.5 V
VDD = 4.0 V VDD = 4.5 V VDD = 5.0 V VDD = 2.5 V 10
20
VDD = 3.0 V VDD = 4.0 V VDD = 4.5 V VDD = 5.0 V VDD = 2.5 V
VDD = 2.0 V VDD = 1.8 V
10
VDD = 2.0 V VDD = 1.8 V
0
0
0.5
1.0
1.5 2.0 VDD - VOH (V)
2.5
3.0
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Low-level output voltage VOL (V)
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CHAPTER 22 CHARACTERISTICS CURVES (REFERENCE VALUES)
22.2 Characteristics Curves for PD78F9418A
10.0 (TA = 25C)
Main system clock operation mode (PCC1 = 0, CSS0 = 0)
Main system clock operation mode (PCC1 = 1, CSS0 = 0) 1.0 Main system clock operation HALT mode (PCC1 = 0, CSS0 = 0) 0.5 Main system clock operation HALT mode (PCC1 = 1, CSS0 = 0)
Supply current IDD (mA)
0.1
Subsystem clock operation mode (CSS0 = 1, MCC = 1)
0.05 Subsystem clock operation HALT mode (CSS0 = 1, MCC = 1)
0.01
0.005
X1
X2 XT1
XT2 220 k
Crystal resonator 5.0 MHz
Crystal resonator 32.768 kHz
22 pF
22 pF VSS
33 pF VSS
33 pF
0.001 0 1 2 3 4 5 6 7 8
Supply voltage VDD (V)
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CHAPTER 23 PACKAGE DRAWINGS
80-PIN PLASTIC QFP (14x14)
A B
60 61
41 40
detail of lead end S C D R Q
80 1
21 20
F J G P H I
M
K S N S L M
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 17.200.20 14.000.20 14.000.20 17.200.20 0.825 0.825 0.320.06 0.13 0.65 (T.P.) 1.600.20 0.800.20 0.17 +0.03 -0.07 0.10 1.400.10 0.1250.075 +7 3 -3 1.70 MAX. P80GC-65-8BT-1
NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition.
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CHAPTER 23 PACKAGE DRAWINGS
80-PIN PLASTIC TQFP (FINE PITCH) (12x12)
A B
60 61
41 40
detail of lead end S C D P T
80 1 F G H I
M
21 20 Q J
R
L U
K S N
NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition.
S
M
ITEM A B C D F G H I J K L M N P Q R S T U
MILLIMETERS 14.00.2 12.00.2 12.00.2 14.00.2 1.25 1.25 0.220.05 0.08 0.5 (T.P.) 1.00.2 0.5 0.1450.05 0.08 1.0 0.10.05 3 +4 -3 1.10.1 0.25 0.60.15 P80GK-50-9EU-1
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CHAPTER 24 RECOMMENDED SOLDERING CONDITIONS
The PD789407A and PD789417A Subseries should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Table 24-1. Surface Mounting Type Soldering Conditions (1/2)
PD789405AGC-xxx-8BT: 80-pin plastic QFP (14 x 14) PD789406AGC-xxx-8BT: 80-pin plastic QFP (14 x 14) PD789407AGC-xxx-8BT: 80-pin plastic QFP (14 x 14) PD789415AGC-xxx-8BT: 80-pin plastic QFP (14 x 14) PD789416AGC-xxx-8BT: 80-pin plastic QFP (14 x 14) PD789417AGC-xxx-8BT: 80-pin plastic QFP (14 x 14) PD78F9418AGC-8BT:
80-pin plastic QFP (14 x 14)
Recommended Condition Symbol IR35-00-2
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Twice or less Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Twice or less Soldering bath temperature: 260C max., Time: 10 seconds max., Count: 1, Preheating temperature: 120C max. (package surface temperature) Pin temperature: 300C max., Time: 3 seconds max. (per pin row)
VPS
VP15-00-2
Wave soldering
WS60-00-1
Partial heating
-
Caution Do not use different soldering methods together (except for partial heating).
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Table 24-1. Surface Mounting Type Soldering Conditions (2/2)
PD789405AGK-xxx-9EU: 80-pin plastic TQFP (fine pitch) (12 x 12) PD789406AGK-xxx-9EU: 80-pin plastic TQFP (fine pitch) (12 x 12) PD789407AGK-xxx-9EU: 80-pin plastic TQFP (fine pitch) (12 x 12) PD789415AGK-xxx-9EU: 80-pin plastic TQFP (fine pitch) (12 x 12) PD789416AGK-xxx-9EU: 80-pin plastic TQFP (fine pitch) (12 x 12) PD789417AGK-xxx-9EU: 80-pin plastic TQFP (fine pitch) (12 x 12) PD78F9418GK-9EU:
80-pin plastic TQFP (fine pitch) (12 x 12)
Recommended Condition Symbol IR35-107-2
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature: 235C, Time: 30 seconds max. (at 210C Note (after that, or higher), Count: Twice or less, Exposure limit: 7 days prebake at 125C for 10 hours)
VPS
Package peak temperature: 215C, Time: 40 seconds max. (at 200C Note (after that, or higher), Count: Twice or less, Exposure limit: 7 days prebake at 125C for 10 hours)
VP15-107-2
Partial heating
Pin temperature: 300C max., Time: 3 seconds max. (per pin row)
-
Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating).
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APPENDIX A DEVELOPMENT TOOLS
The following development tools are available for development of systems using the PD789407A and
PD789417A Subseries.
Figure A-1 shows development tools.
* Support of PC98-NX series
Unless specified otherwise, the products supported by IBM PC/ATTM compatibles can be used in the PC98-NX series. When using the PC98-NX series, refer to the explanation of IBM PC/AT compatibles.
* Windows
Unless specified otherwise, "Windows" indicates the following operating systems. * Windows 3.1 * Windows 95, 98, 2000 * Windows NTTM Ver.4.0
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Figure A-1. Development Tools
Software package
* Software package
Language processing software
Debugging software
* Assembler package * C compiler package * Device file * C library source fileNote 1
* Integrated debugger * System simulator
Control software
* Project Manager
(Windows version only)Note 2
Host machine (PC or EWS)
Interface adapter
Power supply unit Flash memory writing environment Flash programmer In-circuit emulator
Flash memory writing adapter
Emulation board
Flash memory Emulation probe
Conversion socket or conversion adapter Target system
Notes 1. C library source file is not included in the software package. 2. Project Manager is included in the assembler package. Project Manager is used only in the Windows environment.
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A.1 Software Package
SP78K0S Software tools for development of the 78K/0S Series are combined in this package. The following tools are included. RA78K0S, CC78K0S, ID78K0S-NS, SM78K0S, and device files Part number: SxxxxSP78K0S
Software package
Remark
xxxx in the part number differs depending on the operating system to be used.
SxxxxSP78K0S
xxxx AB17 BB17 Host Machine PC-9800 series, IBM PC/AT compatibles OS Japanese Windows English Windows Supply Medium CD-ROM
A.2 Language Processing Software
RA78K0S Assembler package Program that converts program written in mnemonic into object codes that can be executed by microcontroller. In addition, automatic functions to generate a symbol table and optimize branch instructions are also provided. Used in combination with a device file (DF789418) (sold separately). The assembler package is a DOS-based application but may be used in the Windows environment by using the Project Manager of Windows (included in the assembler package). Part number: SxxxxRA78K0S CC78K0S C compiler package Program that converts program written in C language into object codes that can be executed by microcontroller. Used in combination with an assembler package (RA78K0S) and device file (DF789418) (both sold separately). The C compiler package is a DOS-based application but may be used in the Windows environment by using the Project Manager of Windows (included in the assembler package). Part number: SxxxxCC78K0S DF789418 Device file
Note 1
File containing the information inherent to the device. Used in combination with the RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S (all sold separately). Part number: SxxxxDF789418
CC78K0S-L C library source file
Note 2
Source file of functions for generating object library included in C compiler package. Necessary for changing object library included in C compiler package according to customer's specifications. Since this is a source file, its working environment does not depend on any particular operating system. Part number: SxxxxCC78K0S-L
Notes 1. DF789418 is a common file that can be used with RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S. 2. CC78K0S-L is not included in the software package (SP78K0S).
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Remark
xxxx in the part number differs depending on the host machine and operating system to be used.
SxxxxRA78K0S SxxxxCC78K0S
xxxx AB13 BB13 AB17 BB17 3P17 3K17 HP9000 series 700 SPARCstationTM
TM
Host Machine PC-9800 series, IBM PC/AT compatibles
OS Japanese Windows English Windows Japanese Windows English Windows HP-UXTM (Rel. 10.10) SunOSTM (Rel. 4.1.4), SolarisTM (Rel. 2.5.1)
Supply Medium 3.5-inch 2HD FD
CD-ROM
SxxxxDF789418 SxxxxCC78K0S-L
xxxx AB13 BB13 3P16 3K13 3K15 Host Machine PC-9800 series, IBM PC/AT compatibles HP9000 series 700 SPARCstation OS Japanese Windows English Windows HP-UX (Rel. 10.10) SunOS (Rel. 4.1.4), Solaris (Rel. 2.5.1) DAT 3.5-inch 2HD FD 1/4-inch CGMT Supply Medium 3.5-inch 2HD FD
A.3 Control Software
Project Manager Control software created for efficient development of the user program in the Windows environment. User program development operations such as editor startup, build, and debugger startup can be performed from the Project Manager. The Project Manager is included in the assembler package (RA78K0S). The Project Manager is used only in the Windows environment.
A.4 Flash Memory Writing Tools
Flashpro III (FL-PR3, PG-FP3) Flashpro IV (FL-PR4, PG-FP4) Flash programmer FA-80GC-8BT FA-80GK-9EU Flash memory writing adapter Dedicated flash programmer for microcontrollers incorporating flash memory
Adapter for writing to flash memory and connected to Flashpro III or Flashpro IV. * FA-80GC-8BT: For 80-pin plastic QFP (GC-8BT type) * FA-80GK-9EU: For 80-pin plastic TQFP (GK-9EU type)
Remark
The FL-PR3, FL-PR4, FA-80GC-8BT, and FA-80GK-9EU are products made by Naito Densei Machida Mfg. Co., Ltd. (TEL +81-45-475-4191).
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A.5 Debugging Tools (Hardware)
IE-78K0S-NS In-circuit emulator In-circuit emulator for debugging a hardware and software of application system using the 78K/0S Series. Supports an integrated debugger (ID78K0S-NS). Used in combination with an AC adapter, emulation probe, and interface adapter for connecting the host machine. In-circuit emulator with functions expanded from the IE-78K0S-NS. The debug function has been further enhanced with the addition of a coverage function, and enhancement of the tracer function and timer function. Adapter for supplying power from AC 100 to 240 V outlet.
IE-78K0S-NS-A In-circuit emulator
IE-70000-MC-PS-B AC adapter IE-70000-98-IF-C Interface adapter IE-70000-CD-IF-A PC card interface IE-70000-PC-IF-C Interface adapter IE-70000-PCI-IF-A Interface adapter IE-789418-NS-EM1 Emulation board NP-80GC Emulation probe EV-9200GC-80 Conversion socket NP-80GC-TQ NP-H80GC-TQ Emulation probe TGC-080SBP Conversion adapter NP-80GK NP-H80GK-TQ Emulation probe TGK-080SDW Conversion adapter
Adapter necessary when using a PC-9800 series PC (except notebook type) as the host machine of the IE-78K0S-NS (C bus supported) PC card and interface cable necessary when using a notebook PC as the host machine of the IE-78K0S-NS (PCMCIA socket supported) Adapter necessary when using an IBM PC/AT compatible as the host machine of the IE-78K0S-NS (ISA bus supported) Adapter necessary when using a personal computer incorporating the PCI bus as the host machine of the IE-78K0S-NS Board for emulating the peripheral hardware specific to the device. Used in combination with an in-circuit emulator. Cable to connect an in-circuit emulator to the target system. Used in combination with the EV-9200GC-80. Conversion socket to connect the NP-80GC to a target system board on which an 80-pin plastic QFP (GC-8BT type) can be mounted. Cable to connect an in-circuit emulator to the target system. Used in combination with the TGC-080SBP. Conversion adapter to connect the NP-80GC-TQ or NP-H80GC-TQ to a target system board on which an 80-pin plastic QFP (GC-8BT type) can be mounted. Cable to connect an in-circuit emulator to the target system. Used in combination with the TGK-080SDW. Conversion adapter to connect the NP-80GK or NP-H80GK-TQ to a target system board on which an 80-pin plastic TQFP (fine pitch) (GK-9EU type) can be mounted.
Remarks 1. The NP-80GC, NP-80GC-TQ, NP-H80GC-TQ, NP-80GK, and NP-H80GK-TQ are products made by Naito Densei Machida Mfg. Co., Ltd. (TEL +81-45-475-4191). 2. The TGC-080SBP and TGK-080SDW are products made by TOKYO ELETECH CORPORATION. For further information, contact: Daimaru Kogyo, Ltd. Tokyo Electronics Department (TEL +81-3-3820-7112) Osaka Electronics Department (TEL +81-6-6244-6672) 3. The EV-9200GC-80 is sold in five units as a set. 4. The TGC-080SBP and TGK-080SDW are sold in one set units.
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A.6 Debugging Tools (Software)
ID78K0S-NS Integrated debugger This debugger supports the in-circuit emulators IE-78K0S-NS and IE-78K0S-NS-A for the 78K/0S Series. The ID78K0S-NS is Windows-based software. It has improved C-compatible debugging functions and can display the results of tracing with the source program using an integrating window function that associates the source program, disassemble display, and memory display with the trace result. Used in combination with a device file (DF789418) (sold separately). Part number: SxxxxID78K0S-NS SM78K0S System simulator This is a system simulator for the 78K/0S Series. The SM78K0S is Windows-based software. It can be used to debug the target system at C source level or assembler level while simulating the operation of the target system on the host machine. Using SM78K0S, the logic and performance of the application can be verified independently of hardware development. Therefore, the development efficiency can be enhanced and the software quality can be improved. Used in combination with a device file (DF789418) (sold separately). Part number: SxxxxSM78K0S DF789418 Device file
Note
File containing the information inherent to the device. Used in combination with the RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S (all sold separately). Part number: SxxxxDF789418
Note DF789418 is a common file that can be used with RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S. Remark xxxx in the part number differs depending on the operating system and supply medium to be used.
SxxxxID78K0S-NS SxxxxSM78K0S
xxxx AB13 BB13 AB17 BB17 Host Machine PC-9800 series, IBM PC/AT compatibles OS Japanese Windows English Windows Japanese Windows English Windows CD-ROM Supply Medium 3.5-inch 2HD FD
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A.7 Package Drawings of Conversion Socket and Conversion Adapter
A.7.1 Package drawing and recommended footprint of conversion socket (EV-9200GC-80) Figure A-2. Package Drawing of EV-9200GC-80 (for Reference)
Based on EV-9200GC-80 (1) Package drawing (in mm)
A E B F M N O
R D C S J
K
EV-9200GC-80
1
No.1 pin index
P
G H I EV-9200GC-80-G1E ITEM A B C D E F G H I J K L M N O P Q R S MILLIMETERS 18.0 14.4 14.4 18.0 4-C 2.0 0.8 6.0 16.0 18.7 6.0 16.0 18.7 8.2 8.0 2.5 2.0 0.35
2.3 1.5
Q
INCHES 0.709 0.567 0.567 0.709 4-C 0.079 0.031 0.236 0.63 0.736 0.236 0.63 0.736 0.323 0.315 0.098 0.079 0.014
0.091 0.059
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Figure A-3. Recommended Footprint of EV-9200GC-80 (for Reference)
Based on EV-9200GC-80 (2) Pad drawing (in mm)
G
J K
E D F H
L
C B A EV-9200GC-80-P1E ITEM A B C D E F G H I J K L Caution MILLIMETERS 19.7 15.0 0.650.02 x 19=12.350.05 INCHES 0.776 0.591 0.026+0.001 -0.002 x 0.748=0.486 +0.003 -0.002
0.650.02 x 19=12.350.05 0.026 +0.001 x 0.748=0.486 +0.003 -0.002 -0.002 15.0 19.7 6.0 0.05 6.0 0.05 0.35 0.02
2.36 0.03 2.3 1.57 0.03
0.591 0.776 0.236 +0.003 -0.002 0.236 +0.003 -0.002 0.014 +0.001 -0.001
0.093+0.001 -0.002 0.091 0.062+0.001 -0.002
Dimensions of mount pad for EV-9200 and that for target device (QFP) may be different in some parts. For the recommended mount pad dimensions for QFP, refer to "Semiconductor Device Mount Manual" (http://www.necel.com/pkg/en/mount/index.html).
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A.7.2 Package drawing of conversion adapter (TGK-080SDW) Figure A-4. Package Drawing of TGK-080SDW (for Reference)
TGK-080SDW (TQPACK080SD + TQSOCKET080SDW) Package dimension (unit: mm)
A B C D R Q Q Q P S O O O N I JJJ K L L LM gv k j i h p l n m
ITEM A B C D E F G H I J K L M N O P Q R S T U V W X Y Z MILLIMETERS 18.0 11.77 0.5x19=9.5 0.5 0.5x19=9.5 11.77 18.0 0.5 1.58 1.2 7.64 1.2 1.58 1.58 1.2 7.64 1.2 1.58 INCHES 0.709 0.463 0.020x0.748=0.374 0.020 0.020x0.748=0.374 0.463 0.709 0.020 0.062 0.047 0.301 0.047 0.062 0.062 0.047 0.301 0.047 0.062 ITEM a b c d e f g h i j k l m n o p q r s t u v MILLIMETERS 0.5x19=9.50.10 0.25 INCHES 0.020x0.748=0.3740.004 0.010
T
U V
c
e b a
M2 screw
GFE
H
d
W X Y u r t s q
Z
f
Protrusion : 4 places
o
5.3 5.3 1.3 3.55 0.3
1.850.2 3.5 2.0 3.0 0.25 14.0 1.40.2 1.40.2 h=1.8 1.3 0~5 5.9 0.8 2.4 2.7 3.9
0.209 0.209 0.051 0.140 0.012
0.0730.008 0.138 0.079 0.118 0.010 0.551 0.0550.008 0.0550.008 h=0.071 0.051 0.000~0.197 0.232 0.031 0.094 0.106 0.154 TGK-080SDW-G1E
3.55
C 2.0 12.31 10.17 6.8 8.24 14.8 1.40.2
0.140
C 0.079 0.485 0.400 0.268 0.324 0.583 0.0550.008
note: Product by TOKYO ELETECH CORPORATION.
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A.7.3 Package drawing of conversion adapter (TGC-080SBP) Figure A-5. Package Drawing of TGC-080SBP (for Reference)
Reference diagram: TGC-080SBP (TQPACK080SB+TQSOCKET080SBP) Package dimension (unit: mm)
I C A B J K
W
N R GFED L
S Protrusion height T
V
U M
H Y Z g c f b e d h j i k X m l
O P Q
a
note: Product by TOKYO ELETECH CORPORATION.
;
ITEM A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
MILLIMETERS 21.0 0.65x19=12.35 0.65 10.35 12.75 15.15 17.55 14.47 C 2.0 14.95 13.95 13.7 1.15 1.15 12.62 17.52 21.0 5.0 4- 1.3 1.8
INCHES 0.827 0.026x0.748=0.486 0.026 0.407 0.502 0.596 0.691 0.570 C 0.079 0.589 0.549 0.539 0.045 0.045 0.497 0.690 0.827 0.197 4- 0.051 0.071
ITEM a b c d e f g h i j k l m
MILLIMETERS (16.95) 7.35 1.2 1.85 3.5 2.0 6.0 0.25 13.95 1.025 1.025 2.4 2.7
INCHES (0.667) 0.289 0.047 0.073 0.138 0.079 0.236 0.010 0.549 0.040 0.040 0.094 0.106
TGC-080SBP-G0E
5.3
7.7 4-C 1.0
0.209
0.303 4-C 0.039
3.55 0.9 0.3
0.140 0.035 0.012
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APPENDIX B NOTES ON TARGET SYSTEM DESIGN
Figures B-1 to B-4 show the conditions when connecting the emulation probe to the conversion adapter or conversion socket. Follow the configuration below and consider the shape of parts to be mounted on the target system when designing a system. (1) NP-80GC, NP-80GC-TQ, NP-H80GC-TQ Figure B-1. Distance Between In-Circuit Emulator and Conversion Socket (80GC)
In-circuit emulator IE-78K0S-NS or IE-78K0S-NS-A Target system Emulation board IE-789418-NS-EM1 170 mmNote
CN1
Emulation probe NP-80GC, NP-80GC-TQ NP-H80GC-TQ
Conversion socket: EV-9200GC-80 or Conversion adapter: TGC-080SBP
Note
When NP-H80GC-TQ is used, the distance is 370 mm.
Remark NP-80GC, NP-80GC-TQ, and NP-H80GC-TQ are products of Naito Densei Machida Mfg. Co., Ltd.
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Figure B-2. Connection Condition of Target System (NP-80GC-TQ)
Emulation board IE-789418-NS-EM1
Extension probe NP-80GC-TQ
23 mm
Conversion adapter TGC-080SBP
11 mm
40 mm
34 mm
Target system
Remark NP-80GC-TQ is a product of Naito Densei Machida Mfg. Co., Ltd. TGC-080SBP is a product of TOKYO ELETECH CORPORATION.
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(2) NP-80GK, NP-H80GK-TQ Figure B-3. Distance Between In-Circuit Emulator and Conversion Adapter (80GK)
In-circuit emulator IE-78K0S-NS or IE-78K0S-NS-A Target system Emulation board IE-789418-NS-EM1 170 mmNote
CN1
Emulation probe NP-80GK, NP-H80GK-TQ
Conversion adapter TGK-080SDW
Note
When NP-H80GK-TQ is used, the distance is 370 mm.
Remark NP-80GK and NP-H80GK-TQ are products of Naito Densei Machida Mfg. Co., Ltd. TGK-080SDW is a product of TOKYO ELETECH CORPORATION.
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Figure B-4. Connection Condition of Target System (NP-80GK)
Emulation board IE-789418-NS-EM1
Extension probe NP-80GK
23 mm
Conversion adapter TGK-080SDW
11 mm
40 mm
34 mm
Target system
Remark NP-80GK is a product of Naito Densei Machida Mfg. Co., Ltd. TGK-080SDW is a product of TOKYO ELETECH CORPORATION.
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APPENDIX C REGISTER INDEX
C.1 Register Index (Alphabetic Order of Register Name)
[A] A/D conversion result register 0 (ADCR0)....................................................................................................141, 154 A/D converter mode register 0 (ADM0) ........................................................................................................143, 156 A/D input selection register 0 (ADS0)...........................................................................................................144, 157 Asynchronous serial interface mode register 00 (ASIM00) ..........................................................177, 184, 186, 199 Asynchronous serial interface status register 00 (ASIS00) ..........................................................................179, 187 [B] Baud rate generator control register 00 (BRGC00) ..............................................................................180, 188, 200 [C] Comparator mode register 0 (CMPRM0)..............................................................................................................168 [E] 8-bit compare register 00 (CR00) .........................................................................................................................117 8-bit compare register 01 (CR01) .........................................................................................................................117 8-bit compare register 02 (CR02) .........................................................................................................................117 8-bit timer counter 00 (TM00) ...............................................................................................................................117 8-bit timer counter 01 (TM01) ...............................................................................................................................117 8-bit timer counter 02 (TM02) ...............................................................................................................................117 8-bit timer mode control register 00 (TMC00).......................................................................................................118 8-bit timer mode control register 01 (TMC01).......................................................................................................119 8-bit timer mode control register 02 (TMC02).......................................................................................................120 External interrupt mode register 0 (INTM0) ..........................................................................................................234 External interrupt mode register 1 (INTM1) ..........................................................................................................235 [I] Interrupt mask flag register 0 (MK0) .....................................................................................................................233 Interrupt mask flag register 1 (MK1) .....................................................................................................................233 Interrupt request flag register 0 (IF0)....................................................................................................................232 Interrupt request flag register 1 (IF1)....................................................................................................................232 [K] Key return mode register 00 (KRM00)..................................................................................................................237 [L] LCD clock control register 0 (LCDC0) ..................................................................................................................207 LCD display mode register 0 (LCDM0).................................................................................................................205 LCD port selector 0 (LPS0) ..................................................................................................................................206
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[O] Oscillation stabilization time selection register (OSTS)........................................................................................ 245 [P] Port 0 (P0).............................................................................................................................................................. 72 Port 2 (P2).............................................................................................................................................................. 73 Port 4 (P4).............................................................................................................................................................. 78 Port 5 (P5).............................................................................................................................................................. 80 Port 6 (P6).............................................................................................................................................................. 81 Port 8 (P8).............................................................................................................................................................. 83 Port 9 (P9).............................................................................................................................................................. 84 Port mode register 0 (PM0) .................................................................................................................................... 85 Port mode register 2 (PM2) .................................................................................................................... 85, 106, 121 Port mode register 4 (PM4) .................................................................................................................................... 85 Port mode register 5 (PM5) .................................................................................................................................... 85 Port mode register 8 (PM8) .................................................................................................................................... 85 Port mode register 9 (PM9) .................................................................................................................................... 85 Processor clock control register (PCC) .................................................................................................................. 91 Pull-up resistor option register 0 (PU0) .................................................................................................................. 86 Pull-up resistor option register 1 (PU1) .................................................................................................................. 86 Pull-up resistor option register 2 (PU2) .................................................................................................................. 86 [R] Receive buffer register 00 (RXB00) ..................................................................................................................... 175 [S] Serial operation mode register 00 (CSIM00)................................................................................ 176, 183, 185, 198 16-bit capture register 50 (TCP50)....................................................................................................................... 103 16-bit compare register 50 (CR50)....................................................................................................................... 103 16-bit timer counter 50 (TM50)............................................................................................................................. 103 16-bit timer mode control register 50 (TMC50) .................................................................................................... 104 Subclock control register (CSS) ............................................................................................................................. 93 Suboscillation mode register (SCKM) .................................................................................................................... 92 [T] Timer clock selection register 2 (TCL2) ............................................................................................................... 136 Transmit shift register 00 (TXS00) ....................................................................................................................... 175 [W] Watch timer mode control register (WTM) ........................................................................................................... 131 Watchdog timer mode register (WDTM)............................................................................................................... 137
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APPENDIX C REGISTER INDEX
C.2 Register Index (Alphabetic Order of Register Symbol)
[A] ADCR0: ADM0: ADS0: ASIM00: ASIS00: [B] BRGC00: [C] CMPRM0: CR00: CR01: CR02: CR50: CSIM00: CSS: [I] IF0: IF1: INTM0: INTM1: [K] KRM00: [L] LCDC0: LCDM0: LPS0: [M] MK0: MK1: [O] OSTS: [P] P0: P2: P4: P5: P6: Port 0..................................................................................................................................................72 Port 2..................................................................................................................................................73 Port 4..................................................................................................................................................78 Port 5..................................................................................................................................................80 Port 6..................................................................................................................................................81
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A/D conversion result register 0 ...............................................................................................141, 154 A/D converter mode register 0 .................................................................................................143, 156 A/D input selection register 0 ...................................................................................................144, 157 Asynchronous serial interface mode register 00 ......................................................177, 184, 186, 199 Asynchronous serial interface status register 00 .....................................................................179, 187
Baud rate generator control register 00 ...........................................................................180, 188, 200
Comparator mode register 0 ............................................................................................................168 8-bit compare register 00 .................................................................................................................117 8-bit compare register 01 .................................................................................................................117 8-bit compare register 02 .................................................................................................................117 16-bit compare register 50 ...............................................................................................................103 Serial operation mode register 00 ............................................................................176, 183, 185, 198 Subclock control register....................................................................................................................93
Interrupt request flag register 0 ........................................................................................................232 Interrupt request flag register 1 ........................................................................................................232 External interrupt mode register 0....................................................................................................234 External interrupt mode register 1....................................................................................................235
Key return mode register 00.............................................................................................................237
LCD clock control register 0 .............................................................................................................207 LCD display mode register 0............................................................................................................205 LCD port selector 0 ..........................................................................................................................206
Interrupt mask flag register 0 ...........................................................................................................233 Interrupt mask flag register 1 ...........................................................................................................233
Oscillation stabilization time selection register.................................................................................245
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APPENDIX C REGISTER INDEX
P8: P9: PCC: PM0: PM2: PM4: PM5: PM8: PM9: PU0: PU1: PU2: [R] RXB00: [S] SCKM: [T] TCL2: TCP50: TM00: TM01: TM02: TM50: TMC00: TMC01: TMC02: TMC50: TXS00: [W] WDTM: WTM:
Port 8 ................................................................................................................................................. 83 Port 9 ................................................................................................................................................. 84 Processor clock control register......................................................................................................... 91 Port mode register 0 .......................................................................................................................... 85 Port mode register 2 .......................................................................................................... 85, 106, 121 Port mode register 4 .......................................................................................................................... 85 Port mode register 5 .......................................................................................................................... 85 Port mode register 8 .......................................................................................................................... 85 Port mode register 9 .......................................................................................................................... 85 Pull-up resistor option register 0 ........................................................................................................ 86 Pull-up resistor option register 1 ........................................................................................................ 86 Pull-up resistor option register 2 ........................................................................................................ 86
Receive buffer register 00................................................................................................................ 175
Suboscillation mode register.............................................................................................................. 92
Timer clock selection register 2 ....................................................................................................... 136 16-bit capture register 50 ................................................................................................................. 103 8-bit timer counter 00 ....................................................................................................................... 117 8-bit timer counter 01 ....................................................................................................................... 117 8-bit timer counter 02 ....................................................................................................................... 117 16-bit timer counter 50 ..................................................................................................................... 103 8-bit timer mode control register 00 ................................................................................................. 118 8-bit timer mode control register 01 ................................................................................................. 119 8-bit timer mode control register 02 ................................................................................................. 120 16-bit timer mode control register 50 ............................................................................................... 104 Transmit shift register 00 ................................................................................................................. 175
Watchdog timer mode register......................................................................................................... 137 Watch timer mode control register ................................................................................................... 131
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APPENDIX D REVISION HISTORY
Here is the revision history of this manual. The "Applied to:" column indicates the chapters of each edition in which the revision was applied. (1/2)
Edition 2nd Revision from Previous Edition Modification of packages * Deletion of 80-pin plastic TQFP (fine pitch) (GK-BE9 type) * Addition of 80-pin plastic TQFP (fine pitch) (GK-9EU type) Modification of Table 2-1 Types of Pin I/O Circuits Modification of Table 4-3 Port Mode Register and Output Latch Settings When Using Alternate Functions Modification of Caution 2 in 6.2 Configuration of 16-Bit Timer (1) 16-bit compare register 50 (CR50) Modification of Figure 6-2 Format of 16-Bit Timer Mode Control Register 50 Addition of Caution in 6.4.1 Operation as timer interrupt Modification of Figure 6-8 Settings of 16-Bit Timer Mode Control Register 50 for Capture Operation Addition of Caution in 7.4.3 Operation as square-wave output CHAPTER 7 8-BIT TIMER/ EVENT COUNTER CHAPTER 10 8-BIT A/D CONVERTER (PD789407A SUBSERIES) CHAPTER 11 10-BIT A/D CONVERTER (PD789417A SUBSERIES) CHAPTER 18 PD78F9418A Applied to: Throughout
CHAPTER 2 PIN FUNCTIONS CHAPTER 4 PORT FUNCTIONS CHAPTER 6 16-BIT TIMER
Addition of Caution in 10.4.1 Basic operation of 8-bit A/D converter
Addition of Caution in 11.4.1 Basic operation of 10-bit A/D converter
Addition of Caution in Table 18-1 Differences Between PD78F9418A and Mask ROM Versions Modification of Table 18-2 Communication Mode and addition of Note in it Modification of Figure 18-4 Flashpro III Connection Example in Pseudo 3-Wire Mode (When P0 Is Used) Modification of Table 18-4 Example of Settings for PG-FP3 Modification of product name of flash memory programming adapter in A.2 Flash Memory Programming Tools Addition of product name of conversion adapter corresponding to each emulation probe in A.3.1 Hardware 3rd Modification of pin handling of AVREF pin and VPP pin Addition of Note related to feedback resistor
APPENDIX A DEVELOPMENT TOOLS
CHAPTER 2 PIN FUNCTIONS CHAPTER 5 CLOCK GENERATOR CHAPTER 6 16-BIT TIMER 50 CHAPTER 10 8-BIT A/D CONVERTER (PD789407A SUBSERIES)
Addition of 6.5 Cautions on Using 16-Bit Timer 50 Addition of (8) Input impedance of ANI0 to ANI6 pins in 10.5 Cautions on Using 8-Bit A/D Converter
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APPENDIX D REVISION HISTORY
(2/2)
Edition 3rd Revision from Previous Edition Modification of description of (2) A/D conversion result register 0 (ADCR0) in 11.2 Configuration of 10-Bit A/D Converter Addition of (8) Input impedance of ANI0 to ANI6 pins in 11.5 Cautions on Using 10-Bit A/D Converter Addition of description on reading receive data of UART Applied to: CHAPTER 11 10-BIT A/D CONVERTER (PD789417A SUBSERIES)
CHAPTER 13 SERIAL INTERFACE 00 CHAPTER 15 INTERRUPT FUNCTIONS CHAPTER 18 PD78F9418A
Addition of Caution in Figure 15-2 Format of Interrupt Request Flag Register Addition of Caution in Figure 15-7 Format of Key Return Mode Register 00 Addition of description on pull-up resistor and divider resistor for LCD driving in Table 18-1 Differences Between PD78F9418A and Mask ROM Versions Overall revision of contents related to flash memory programming as 18.1 Flash Memory Characteristics Addition of electrical specifications
CHAPTER 21 ELECTRICAL SPECIFICATIONS CHAPTER 22 CHARACTERISTICS CURVES (REFERENCE VALUES) CHAPTER 23 PACKAGE DRAWINGS CHAPTER 24 RECOMMENDED SOLDERING CONDITIONS APPENDIX A DEVELOPMENT TOOLS APPENDIX B NOTES ON TARGET SYSTEM DESIGN
Addition of characteristics curves (reference values)
Addition of package drawings
Addition of recommended soldering conditions
Overall revision of contents of development tools Deletion of embedded software Addition of notes on target system design
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